Silicon quantum dots in a MOSFET structure: Level structure

M. Khoury, A. Gunther, M. J. Rack, D. P. Pivin, D. K. Ferry

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Silicon quantum dot devices based on a dual gate technique in a silicon MOS technology are fabricated. Two lateral gates deplete the inversion layer which is induced by a top gate, thus forming a quantum dot. The dot is located between the source and drain of a long channel MOSFET. The dot is fabricated with a 9 nm thermal oxide, deposition of the lateral gates, a 60 nm plasma enhanced chemical vapor deposited oxide and Al top gates. Lithographic dimensions of the dots ranged from 200 nm to 40 nm, and these are defined by high resolution electron beam lithography.

Original languageEnglish (US)
Title of host publicationAnnual Device Research Conference Digest
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages82-83
Number of pages2
StatePublished - 1999
EventProceedings of the 1999 57th Annual Device Research Conference Digest (DRC) - Santa Barbara, CA, USA
Duration: Jun 28 1999Jun 30 1999

Other

OtherProceedings of the 1999 57th Annual Device Research Conference Digest (DRC)
CitySanta Barbara, CA, USA
Period6/28/996/30/99

ASJC Scopus subject areas

  • Engineering(all)

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