Abstract
Silicon quantum dot devices based on a dual gate technique in a silicon MOS technology are fabricated. Two lateral gates deplete the inversion layer which is induced by a top gate, thus forming a quantum dot. The dot is located between the source and drain of a long channel MOSFET. The dot is fabricated with a 9 nm thermal oxide, deposition of the lateral gates, a 60 nm plasma enhanced chemical vapor deposited oxide and Al top gates. Lithographic dimensions of the dots ranged from 200 nm to 40 nm, and these are defined by high resolution electron beam lithography.
| Original language | English (US) |
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| Title of host publication | Annual Device Research Conference Digest |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 82-83 |
| Number of pages | 2 |
| State | Published - 1999 |
| Event | Proceedings of the 1999 57th Annual Device Research Conference Digest (DRC) - Santa Barbara, CA, USA Duration: Jun 28 1999 → Jun 30 1999 |
Other
| Other | Proceedings of the 1999 57th Annual Device Research Conference Digest (DRC) |
|---|---|
| City | Santa Barbara, CA, USA |
| Period | 6/28/99 → 6/30/99 |
ASJC Scopus subject areas
- General Engineering