SET tolerant CMOS comparator

E. Mikkola, B. Vermeire, H. J. Barnaby, H. G. Parks, K. Borhani

Research output: Contribution to journalArticle

22 Scopus citations

Abstract

A novel way to mitigate single event transients (SETs) in a comparator by using auto-zeroing techniques is presented. Two comparators, a folded cascode comparator and a novel auto-zeroed comparator, are simulated using a current pulse model for a single event strike. These simulations show that the novel auto-zeroed comparator transients are never longer in duration than a single auto-zero clock period. This compares favorably to a folded cascode comparator sample circuit, whose maximum transient duration is strongly dependent on the differential input voltage and can be four times as long. The use of the presented auto zero comparator can practically eliminate the comparator contribution to single event errors in many mixed signal circuits, such as analog-to-digital converters (ADCs).

Original languageEnglish (US)
Pages (from-to)3609-3614
Number of pages6
JournalIEEE Transactions on Nuclear Science
Volume51
Issue number6 II
DOIs
StatePublished - Dec 1 2004
Externally publishedYes

Keywords

  • Analog-to-digital converters (ADCs)
  • Auto-zeroing techniques
  • CMOS mixed signal circuits
  • Comparators
  • Folded cascode
  • Hardening-by-design
  • Hardness by design
  • Radiation hardening
  • Single-event effects (SEEs)
  • Single-event transients (SETs)

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Mikkola, E., Vermeire, B., Barnaby, H. J., Parks, H. G., & Borhani, K. (2004). SET tolerant CMOS comparator. IEEE Transactions on Nuclear Science, 51(6 II), 3609-3614. https://doi.org/10.1109/TNS.2004.839161