Semiconductor wafer fabrication subproblem solution procedures for the shifting bottleneck heuristic

W. Matthew Carlyle, John Fowler, Michele Pfund, Hari Balasubramanian, Amit Gadkari

Research output: Contribution to journalArticle

Abstract

At each major iteration, the shifting bottleneck heuristic for job shop scheduling requires the solution of several subproblems - one for each currently unscheduled toolgroup. We discuss an effort to provide a library of subproblem solution procedures for use in a modified shifting-bottleneck heuristic that has been customized for the semiconductor wafer fabrication problem. These procedures are tailored to the toolgroups commonly encountered in wafer fab. We outline the main categories of subproblems encountered in this setting and the corresponding algorithms employed.

Original languageEnglish (US)
Pages (from-to)1-4
Number of pages4
JournalTechnical Paper - Society of Manufacturing Engineers. MF
Issue numberMF02-269
StatePublished - 2002

Fingerprint

Semiconductor materials
Fabrication
Job shop scheduling

Keywords

  • Scheduling
  • Semiconductor manufacturing
  • Shifting bottlenecks heuristic

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering

Cite this

Semiconductor wafer fabrication subproblem solution procedures for the shifting bottleneck heuristic. / Carlyle, W. Matthew; Fowler, John; Pfund, Michele; Balasubramanian, Hari; Gadkari, Amit.

In: Technical Paper - Society of Manufacturing Engineers. MF, No. MF02-269, 2002, p. 1-4.

Research output: Contribution to journalArticle

Carlyle, W. Matthew ; Fowler, John ; Pfund, Michele ; Balasubramanian, Hari ; Gadkari, Amit. / Semiconductor wafer fabrication subproblem solution procedures for the shifting bottleneck heuristic. In: Technical Paper - Society of Manufacturing Engineers. MF. 2002 ; No. MF02-269. pp. 1-4.
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