Semiconductor corner lot generation robust to process variation: Modeling and analysis

Product characterization is an important phase in developing new semiconductors. The goal is to determine if the new product will function when produced under the extreme edge of fabrication variation; if not, the product might be considered to have insufficient design margin, necessitating circuit redesign. Achieving this goal requires producing a so-called corner lot that consists of skew chips; i.e., chips whose key performance parameters that are expected to be around certain targeted extreme values. These skew chips are extensively tested to determine whether their functions still meet specifications. However, due to extensive variation in the fabrication process, few skewed chips can be guaranteed in a produced corner lot, and this is a long-standing frustration in the semiconductor industry. One approach to produce a satisfactory corner lot is through variation reduction of the fabrication process. Despite being a popular research area, variation reduction is a long-term effort that involves both technical and managerial considerations. We approach this problem from a different avenue by treating process variation as given and instead identifying a design strategy that guarantees production of a good corner lot robust to the variation. Specifically, we propose a first-of-its-kind rigorous mathematical formulation about this problem, investigate the theoretical properties and practical implications of this formulation, and further propose several optimal criteria and a corresponding design search algorithm. Applications to a broad range of semiconductor products are presented to demonstrate the universal improvement of the proposed optimal design compared with the traditional design used in current industrial practice.