Self-timed redundant-binary number to binary number converter for digital arithmetic processors

Chin Long Wey, Haiyan Wang, Cheng Ping Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper presents a self-timed converter circuit which converts an n-digit redundant binary number to an (n + l)-bit binary number. Self-timed refers to the fact that the conversion is problem-dependent and requires variable conversion time to complete the operation. The propagation delay of the proposed converter circuit does not increase with the number of digits to be converted, but it is determined by the maximum number of consecutive O's in that number. This study shows that the statistical upper bound of the average maximum number of consecutive O's is log3n, or 3.78 for 64-digits. This implies that the proposed self-time circuit can be approximately 17 times faster than the ripple-type converter. Thus, the proposed converter is well-suited to high-speed, long-word digital arithmetic processors.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages386-391
Number of pages6
StatePublished - 1995
Externally publishedYes
EventProceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA
Duration: Oct 2 1995Oct 4 1995

Other

OtherProceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityAustin, TX, USA
Period10/2/9510/4/95

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Wey, C. L., Wang, H., & Wang, C. P. (1995). Self-timed redundant-binary number to binary number converter for digital arithmetic processors. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 386-391). IEEE.