Abstract

To understand the impact of self-heating in SOI CMOS technologies we have fabricated pairs of 40nm gate length n-channel MOSFETs that share a common source contact and the same active silicon region. One of the MOSFETs is turned on and heats the active silicon, while the other is biased into the subthreshold regime and operates as a local thermometer. Preliminary results show that the MOSFET thermometer temperature increases approximately quadratically with the power dissipated in the MOSFET heater.

Original languageEnglish (US)
Title of host publication2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538610169
DOIs
Publication statusPublished - Jan 8 2019
Event13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 - Portland, United States
Duration: Oct 14 2018Oct 17 2018

Publication series

Name2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

Conference

Conference13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018
CountryUnited States
CityPortland
Period10/14/1810/17/18

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Keywords

  • CMOS
  • RFIC
  • self-heating effects
  • silicon-on-insulator
  • sub-threshold operation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Instrumentation

Cite this

Self-heating in SOI MOSFETs at the 45nm node. / Zhang, Xiong; Mehr, Payam; Vasileska, Dragica; Thornton, Trevor.

2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8605870 (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution