Self-heating in SOI MOSFETs at the 45nm node

Xiong Zhang; Payam Mehr; Dragica Vasileska; Trevor Thornton

doi:10.1109/NMDC.2018.8605870

Self-heating in SOI MOSFETs at the 45nm node

Xiong Zhang, Payam Mehr, Dragica Vasileska, Trevor Thornton

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

To understand the impact of self-heating in SOI CMOS technologies we have fabricated pairs of 40nm gate length n-channel MOSFETs that share a common source contact and the same active silicon region. One of the MOSFETs is turned on and heats the active silicon, while the other is biased into the subthreshold regime and operates as a local thermometer. Preliminary results show that the MOSFET thermometer temperature increases approximately quadratically with the power dissipated in the MOSFET heater.

Original language	English (US)
Title of host publication	2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538610169
DOIs	https://doi.org/10.1109/NMDC.2018.8605870
State	Published - Jan 8 2019
Event	13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 - Portland, United States Duration: Oct 14 2018 → Oct 17 2018

Publication series

Name	2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

Conference

Conference	13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018
Country/Territory	United States
City	Portland
Period	10/14/18 → 10/17/18

Keywords

CMOS
RFIC
self-heating effects
silicon-on-insulator
sub-threshold operation

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Surfaces, Coatings and Films
Instrumentation

Access to Document

10.1109/NMDC.2018.8605870

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Self-heating in SOI MOSFETs at the 45nm node. / Zhang, Xiong; Mehr, Payam; Vasileska, Dragica ; Thornton, Trevor.

2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8605870 (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, X, Mehr, P, Vasileska, D & Thornton, T 2019, Self-heating in SOI MOSFETs at the 45nm node. in 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018., 8605870, 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018, Institute of Electrical and Electronics Engineers Inc., 13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018, Portland, United States, 10/14/18. https://doi.org/10.1109/NMDC.2018.8605870

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title = "Self-heating in SOI MOSFETs at the 45nm node",

abstract = "To understand the impact of self-heating in SOI CMOS technologies we have fabricated pairs of 40nm gate length n-channel MOSFETs that share a common source contact and the same active silicon region. One of the MOSFETs is turned on and heats the active silicon, while the other is biased into the subthreshold regime and operates as a local thermometer. Preliminary results show that the MOSFET thermometer temperature increases approximately quadratically with the power dissipated in the MOSFET heater.",

keywords = "CMOS, RFIC, self-heating effects, silicon-on-insulator, sub-threshold operation",

author = "Xiong Zhang and Payam Mehr and Dragica Vasileska and Trevor Thornton",

note = "Funding Information: ACKNOWLEDGMENT The authors thank Ned Cahoon and Chaojiang Li of Global Foundries for providing access to the 45RFSOI technology. Access to the ASU Nanofab and associated laboratories was supported, in part, by NSF contract ECCS-1542160. Publisher Copyright: {\textcopyright} 2018 IEEE.; 13th IEEE Nanotechnology Materials and Devices Conference, NMDC 2018 ; Conference date: 14-10-2018 Through 17-10-2018",

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doi = "10.1109/NMDC.2018.8605870",

language = "English (US)",

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AU - Zhang, Xiong

AU - Mehr, Payam

AU - Vasileska, Dragica

AU - Thornton, Trevor

N1 - Funding Information: ACKNOWLEDGMENT The authors thank Ned Cahoon and Chaojiang Li of Global Foundries for providing access to the 45RFSOI technology. Access to the ASU Nanofab and associated laboratories was supported, in part, by NSF contract ECCS-1542160. Publisher Copyright: © 2018 IEEE.

PY - 2019/1/8

Y1 - 2019/1/8

N2 - To understand the impact of self-heating in SOI CMOS technologies we have fabricated pairs of 40nm gate length n-channel MOSFETs that share a common source contact and the same active silicon region. One of the MOSFETs is turned on and heats the active silicon, while the other is biased into the subthreshold regime and operates as a local thermometer. Preliminary results show that the MOSFET thermometer temperature increases approximately quadratically with the power dissipated in the MOSFET heater.

AB - To understand the impact of self-heating in SOI CMOS technologies we have fabricated pairs of 40nm gate length n-channel MOSFETs that share a common source contact and the same active silicon region. One of the MOSFETs is turned on and heats the active silicon, while the other is biased into the subthreshold regime and operates as a local thermometer. Preliminary results show that the MOSFET thermometer temperature increases approximately quadratically with the power dissipated in the MOSFET heater.

KW - CMOS

KW - RFIC

KW - self-heating effects

KW - silicon-on-insulator

KW - sub-threshold operation

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T3 - 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

BT - 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 14 October 2018 through 17 October 2018

ER -

Self-heating in SOI MOSFETs at the 45nm node

Abstract

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Keywords

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