Abstract

In this paper we present simulation results obtained with our electro-thermal particle-based device simulator for 25 nm fully depleted silicon-on-insulator devices with (100) and (110) crystallographic orientations. We also investigate the importance of the proper choice of the thermal conductivity model (which is particularly important for thin silicon films) in properly predicting the average maximum temperature and the maximum temperature in the hot spot which are important parameters regarding device reliability.

Original languageEnglish (US)
Title of host publication2012 15th International Workshop on Computational Electronics, IWCE 2012
DOIs
StatePublished - Sep 27 2012
Event2012 15th International Workshop on Computational Electronics, IWCE 2012 - Madison, WI, United States
Duration: May 22 2012May 25 2012

Publication series

Name2012 15th International Workshop on Computational Electronics, IWCE 2012

Other

Other2012 15th International Workshop on Computational Electronics, IWCE 2012
CountryUnited States
CityMadison, WI
Period5/22/125/25/12

    Fingerprint

Keywords

  • Silicon-On-Insulator devices
  • crystallographic orientations
  • electro-thermal particle based device simulation
  • thermal conductivity

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Raleva, K., Vasileska, D., & Goodnick, S. (2012). Self-heating and current degradation in 25 nm FD SOI devices with (100) and (110) crystallographic orientation. In 2012 15th International Workshop on Computational Electronics, IWCE 2012 [6242855] (2012 15th International Workshop on Computational Electronics, IWCE 2012). https://doi.org/10.1109/IWCE.2012.6242855