Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology

Lawrence T Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh Barnaby, Matthew Marinella

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Area efficient self-correcting flip-flops for use with triple modular redundant (TMR) soft-error hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop slave latches self-correct in the clock low phase using Muller C-elements in the latch feedback. These C-elements are driven by the two redundant stored values and not by the slave latch itself, saving area over a similar implementation using majority gate feedback. These flip-flops are implemented as large shift-register arrays on a test chip and have been experimentally tested for their soft-error mitigation in static and dynamic modes of operation using heavy ions and protons. We show how high clock skew can result in susceptibility to soft-errors in the dynamic mode, and explain the potential failure mechanism.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1205-1209
Number of pages5
ISBN (Electronic)9781665484855
DOIs
StatePublished - 2022
Event2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States
Duration: May 27 2022Jun 1 2022

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2022-May
ISSN (Print)0271-4310

Conference

Conference2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Country/TerritoryUnited States
CityAustin
Period5/27/226/1/22

Keywords

  • heavy ion testing
  • proton testing
  • radiation hardening
  • soft errors
  • triple modular redundancy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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