Self-checking and self-diagnosing 32-bit microprocessor multiplier

Mahmut Yilmaz, Derek R. Hower, Sule Ozev, Daniel J. Sorin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P). Our fault tolerant multiplier designs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty subunit off-line. We utilize the branch misprediction recovery mechanism in the microprocessor core to take the error detection process off the critical path. Our analysis shows that our scheme provides 99% fault security and, compared to a baseline unprotected multiplier, achieves this fault tolerance with low performance overhead (5% for NP and 2.5% for P multiplier) and reasonably low area (38% NP and 26% P) and power consumption (36% NP and 28.5% P) overheads.

Original languageEnglish (US)
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
DOIs
StatePublished - Jan 1 2006
Externally publishedYes
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 22 2006Oct 27 2006

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

Other2006 IEEE International Test Conference, ITC
CountryUnited States
CitySanta Clara, CA
Period10/22/0610/27/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • Cite this

    Yilmaz, M., Hower, D. R., Ozev, S., & Sorin, D. J. (2006). Self-checking and self-diagnosing 32-bit microprocessor multiplier. In 2006 IEEE International Test Conference, ITC [4079312] (Proceedings - International Test Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2006.297634