Selectively Doped Heterostructure Frequency Dividers

Richard Kiehl, M. D. Feuer, R. H. Hendel, V. G. Keramidas, C. L. Allyn, R. Dingle, J. C M Hwang

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having l-μm gate lengths and 4-μm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al.3Ga.7As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.

Original languageEnglish (US)
Pages (from-to)377-379
Number of pages3
JournalIEEE Electron Device Letters
Volume4
Issue number10
DOIs
StatePublished - 1983
Externally publishedYes

Fingerprint

Heterojunctions
Energy dissipation
Electron transport properties
Logic gates
Networks (circuits)
Flip flop circuits
Electron mobility
Field effect transistors
Molecular beam epitaxy
Lithography
Buffers
gallium arsenide

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Engineering(all)

Cite this

Kiehl, R., Feuer, M. D., Hendel, R. H., Keramidas, V. G., Allyn, C. L., Dingle, R., & Hwang, J. C. M. (1983). Selectively Doped Heterostructure Frequency Dividers. IEEE Electron Device Letters, 4(10), 377-379. https://doi.org/10.1109/EDL.1983.25770

Selectively Doped Heterostructure Frequency Dividers. / Kiehl, Richard; Feuer, M. D.; Hendel, R. H.; Keramidas, V. G.; Allyn, C. L.; Dingle, R.; Hwang, J. C M.

In: IEEE Electron Device Letters, Vol. 4, No. 10, 1983, p. 377-379.

Research output: Contribution to journalArticle

Kiehl, R, Feuer, MD, Hendel, RH, Keramidas, VG, Allyn, CL, Dingle, R & Hwang, JCM 1983, 'Selectively Doped Heterostructure Frequency Dividers', IEEE Electron Device Letters, vol. 4, no. 10, pp. 377-379. https://doi.org/10.1109/EDL.1983.25770
Kiehl R, Feuer MD, Hendel RH, Keramidas VG, Allyn CL, Dingle R et al. Selectively Doped Heterostructure Frequency Dividers. IEEE Electron Device Letters. 1983;4(10):377-379. https://doi.org/10.1109/EDL.1983.25770
Kiehl, Richard ; Feuer, M. D. ; Hendel, R. H. ; Keramidas, V. G. ; Allyn, C. L. ; Dingle, R. ; Hwang, J. C M. / Selectively Doped Heterostructure Frequency Dividers. In: IEEE Electron Device Letters. 1983 ; Vol. 4, No. 10. pp. 377-379.
@article{6dbe025b8b62431fbe10cccea36a62ff,
title = "Selectively Doped Heterostructure Frequency Dividers",
abstract = "The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having l-μm gate lengths and 4-μm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al.3Ga.7As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.",
author = "Richard Kiehl and Feuer, {M. D.} and Hendel, {R. H.} and Keramidas, {V. G.} and Allyn, {C. L.} and R. Dingle and Hwang, {J. C M}",
year = "1983",
doi = "10.1109/EDL.1983.25770",
language = "English (US)",
volume = "4",
pages = "377--379",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - Selectively Doped Heterostructure Frequency Dividers

AU - Kiehl, Richard

AU - Feuer, M. D.

AU - Hendel, R. H.

AU - Keramidas, V. G.

AU - Allyn, C. L.

AU - Dingle, R.

AU - Hwang, J. C M

PY - 1983

Y1 - 1983

N2 - The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having l-μm gate lengths and 4-μm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al.3Ga.7As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.

AB - The operation of high-speed divide-by-two circuit (binary counter) composed of selectively doped heterostructure logic gates is reported for the first time. These field-effect transistor circuits utilize the enhanced transport properties of high-mobility electrons confined near a heterojunction interface in a selectively doped AlGaAs/GaAs structure. The dividers are based on a Type-D flip-flop composed of six direct-coupled NOR-gates having l-μm gate lengths and 4-μm source-drain spacings. They are fabricated by conventional optical contact lithography on a four-layer Al.3Ga.7As/GaAs structure grown by molecular-beam epitaxy. Successful operation is demonstrated at 5.9 GHz at 77 K for 1.3-V bias and 30-mW total power dissipation (including output buffers) and 3.7 GHz at 300 K for 1.4-V bias and 19-mW total power dissipation. Total power dissipation values as low as 3.9 mW at 0.65-V bias were also obtained for 2.85-GHz operation at 300 K. These preliminary results illustrate the promise of SDHT logic for ultrahigh-speed low-power applications.

UR - http://www.scopus.com/inward/record.url?scp=0020831391&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0020831391&partnerID=8YFLogxK

U2 - 10.1109/EDL.1983.25770

DO - 10.1109/EDL.1983.25770

M3 - Article

VL - 4

SP - 377

EP - 379

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 10

ER -