Scheduling of synchronous data flow models on scratchpad memory based embedded processors

Weijia Che, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Many embedded processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages205-212
Number of pages8
DOIs
StatePublished - 2010
Event2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States
Duration: Nov 7 2010Nov 11 2010

Other

Other2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
CountryUnited States
CitySan Jose, CA
Period11/7/1011/11/10

Fingerprint

Scheduling
Data storage equipment
Linear programming
Embedded systems
Electric power utilization
Specifications
Processing

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

Cite this

Che, W., & Chatha, K. S. (2010). Scheduling of synchronous data flow models on scratchpad memory based embedded processors. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 205-212). [5654150] https://doi.org/10.1109/ICCAD.2010.5654150

Scheduling of synchronous data flow models on scratchpad memory based embedded processors. / Che, Weijia; Chatha, Karam S.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2010. p. 205-212 5654150.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Che, W & Chatha, KS 2010, Scheduling of synchronous data flow models on scratchpad memory based embedded processors. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD., 5654150, pp. 205-212, 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, United States, 11/7/10. https://doi.org/10.1109/ICCAD.2010.5654150
Che W, Chatha KS. Scheduling of synchronous data flow models on scratchpad memory based embedded processors. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2010. p. 205-212. 5654150 https://doi.org/10.1109/ICCAD.2010.5654150
Che, Weijia ; Chatha, Karam S. / Scheduling of synchronous data flow models on scratchpad memory based embedded processors. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2010. pp. 205-212
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