Abstract
Power consumption in memory-intensive operations can be reduced by minimizing the number of memory access. In this paper we describe two scheduling schemes under fixed hardware resource constraints which reduce the number of memory accesses by minimizing the number of intermediate variables that need to be stored. While the first scheme achieves this by post order traversal of the DFG, the second scheme achieves this by judiciously delaying the scheduling of some of the nodes. Experimental results show that these schemes require significantly fewer memory accesses compared to existing scheduling schemes.
| Original language | English (US) |
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| Title of host publication | IEEE Workshop on VLSI Signal Processing, Proceedings |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 169-178 |
| Number of pages | 10 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing - San Francisco, CA, USA Duration: Oct 30 1996 → Nov 1 1996 |
Other
| Other | Proceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing |
|---|---|
| City | San Francisco, CA, USA |
| Period | 10/30/96 → 11/1/96 |
ASJC Scopus subject areas
- Signal Processing