Scheduling for minimizing the number of memory accesses in low power applications

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Power consumption in memory-intensive operations can be reduced by minimizing the number of memory access. In this paper we describe two scheduling schemes under fixed hardware resource constraints which reduce the number of memory accesses by minimizing the number of intermediate variables that need to be stored. While the first scheme achieves this by post order traversal of the DFG, the second scheme achieves this by judiciously delaying the scheduling of some of the nodes. Experimental results show that these schemes require significantly fewer memory accesses compared to existing scheduling schemes.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on VLSI Signal Processing, Proceedings
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages169-178
Number of pages10
StatePublished - 1996
EventProceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing - San Francisco, CA, USA
Duration: Oct 30 1996Nov 1 1996

Other

OtherProceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing
CitySan Francisco, CA, USA
Period10/30/9611/1/96

ASJC Scopus subject areas

  • Signal Processing

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  • Cite this

    Saied, R., & Chakrabarti, C. (1996). Scheduling for minimizing the number of memory accesses in low power applications. In IEEE Workshop on VLSI Signal Processing, Proceedings (pp. 169-178). IEEE.