Scaling-up resistive synaptic arrays for neuro-inspired architecture

Challenges and prospect

Shimeng Yu, Pai Yu Chen, Yu Cao, Lixue Xia, Yu Wang, Huaqiang Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

63 Citations (Scopus)

Abstract

The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuro-inspired architecture.

Original languageEnglish (US)
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17.3.1-17.3.4
Volume2016-February
ISBN (Print)9781467398930
DOIs
StatePublished - Feb 16 2016
Event61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States
Duration: Dec 7 2015Dec 9 2015

Other

Other61st IEEE International Electron Devices Meeting, IEDM 2015
CountryUnited States
CityWashington
Period12/7/1512/9/15

Fingerprint

scaling
Networks (circuits)
learning
Learning algorithms
Macros
Simulators
simulators
chips
trends

Keywords

  • crossbar array
  • machine learning
  • neuromorphic computing
  • Resistive memory
  • synaptic device

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Yu, S., Chen, P. Y., Cao, Y., Xia, L., Wang, Y., & Wu, H. (2016). Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. In Technical Digest - International Electron Devices Meeting, IEDM (Vol. 2016-February, pp. 17.3.1-17.3.4). [7409718] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409718

Scaling-up resistive synaptic arrays for neuro-inspired architecture : Challenges and prospect. / Yu, Shimeng; Chen, Pai Yu; Cao, Yu; Xia, Lixue; Wang, Yu; Wu, Huaqiang.

Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February Institute of Electrical and Electronics Engineers Inc., 2016. p. 17.3.1-17.3.4 7409718.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yu, S, Chen, PY, Cao, Y, Xia, L, Wang, Y & Wu, H 2016, Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. in Technical Digest - International Electron Devices Meeting, IEDM. vol. 2016-February, 7409718, Institute of Electrical and Electronics Engineers Inc., pp. 17.3.1-17.3.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 12/7/15. https://doi.org/10.1109/IEDM.2015.7409718
Yu S, Chen PY, Cao Y, Xia L, Wang Y, Wu H. Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. In Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February. Institute of Electrical and Electronics Engineers Inc. 2016. p. 17.3.1-17.3.4. 7409718 https://doi.org/10.1109/IEDM.2015.7409718
Yu, Shimeng ; Chen, Pai Yu ; Cao, Yu ; Xia, Lixue ; Wang, Yu ; Wu, Huaqiang. / Scaling-up resistive synaptic arrays for neuro-inspired architecture : Challenges and prospect. Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February Institute of Electrical and Electronics Engineers Inc., 2016. pp. 17.3.1-17.3.4
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