Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Shimeng Yu, Pai Yu Chen, Yu Cao, Lixue Xia, Yu Wang, Huaqiang Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

90 Scopus citations

Abstract

The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuro-inspired architecture.

Original languageEnglish (US)
Title of host publication2015 IEEE International Electron Devices Meeting, IEDM 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17.3.1-17.3.4
ISBN (Electronic)9781467398930
DOIs
StatePublished - Feb 16 2015
Event61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States
Duration: Dec 7 2015Dec 9 2015

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2016-February
ISSN (Print)0163-1918

Other

Other61st IEEE International Electron Devices Meeting, IEDM 2015
CountryUnited States
CityWashington
Period12/7/1512/9/15

Keywords

  • Resistive memory
  • crossbar array
  • machine learning
  • neuromorphic computing
  • synaptic device

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Yu, S., Chen, P. Y., Cao, Y., Xia, L., Wang, Y., & Wu, H. (2015). Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 17.3.1-17.3.4). [7409718] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409718