Scaling theory in modern VLSI: Factors affecting interconnects, wire length, and clock speed

D. K. Ferry, L. A. Akers

Research output: Contribution to journalArticle

11 Citations (Scopus)
Original languageEnglish (US)
Pages (from-to)41-44
Number of pages4
JournalIEEE Circuits and Devices Magazine
Volume13
Issue number5
DOIs
StatePublished - Sep 1997

Fingerprint

electric wire
Electric wire
Timing circuits
Interconnection networks (circuit switching)
very large scale integration
clocks
Clocks
wire
Wire
scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

Cite this

Scaling theory in modern VLSI : Factors affecting interconnects, wire length, and clock speed. / Ferry, D. K.; Akers, L. A.

In: IEEE Circuits and Devices Magazine, Vol. 13, No. 5, 09.1997, p. 41-44.

Research output: Contribution to journalArticle

@article{b6eadbe55b804037b066af1548d891c9,
title = "Scaling theory in modern VLSI: Factors affecting interconnects, wire length, and clock speed",
author = "Ferry, {D. K.} and Akers, {L. A.}",
year = "1997",
month = "9",
doi = "10.1109/101.621606",
language = "English (US)",
volume = "13",
pages = "41--44",
journal = "IEEE Circuits and Devices Magazine",
issn = "8755-3996",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - Scaling theory in modern VLSI

T2 - Factors affecting interconnects, wire length, and clock speed

AU - Ferry, D. K.

AU - Akers, L. A.

PY - 1997/9

Y1 - 1997/9

UR - http://www.scopus.com/inward/record.url?scp=0031232996&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031232996&partnerID=8YFLogxK

U2 - 10.1109/101.621606

DO - 10.1109/101.621606

M3 - Article

AN - SCOPUS:0031232996

VL - 13

SP - 41

EP - 44

JO - IEEE Circuits and Devices Magazine

JF - IEEE Circuits and Devices Magazine

SN - 8755-3996

IS - 5

ER -