D. K. Ferry, L. A. Akers
Research output: Contribution to journal › Article › peer-review
Scaling theory in modern VLSI : Factors affecting interconnects, wire length, and clock speed. / Ferry, D. K.; Akers, L. A.
TY - JOUR
T1 - Scaling theory in modern VLSI
T2 - Factors affecting interconnects, wire length, and clock speed
AU - Ferry, D. K.
AU - Akers, L. A.
N1 - Funding Information:
The authors have benefited from discussions with J.R. Barker and P. Hasler. This work was supported in part by the Defense Advanced Research Projects Agency.
PY - 1997/9
Y1 - 1997/9
UR - http://www.scopus.com/inward/record.url?scp=0031232996&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0031232996&partnerID=8YFLogxK
U2 - 10.1109/101.621606
DO - 10.1109/101.621606
M3 - Article
AN - SCOPUS:0031232996
VL - 13
SP - 41
EP - 44
JO - IEEE Circuits and Devices Magazine
JF - IEEE Circuits and Devices Magazine
SN - 8755-3996
IS - 5