Abstract

Metalsemiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ∼70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg < 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200300 nm.

Original languageEnglish (US)
Article number5765667
Pages (from-to)1628-1634
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume58
Issue number6
DOIs
StatePublished - Jun 2011

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Field effect transistors
Metals
Gates (transistor)
Silicon
Demonstrations
Oxide semiconductors

Keywords

  • Metalsemiconductor field-effect transistors (MESFETs)
  • partially depleted (PD)
  • Schottky junction
  • silicon-on-insulator (SOI)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lepkowski, W., Ghajar, M. R., Wilk, S. J., Summers, N., Thornton, T., & Fechner, P. S. (2011). Scaling SOI MESFETs to 150-nm CMOS technologies. IEEE Transactions on Electron Devices, 58(6), 1628-1634. [5765667]. https://doi.org/10.1109/TED.2011.2125965

Scaling SOI MESFETs to 150-nm CMOS technologies. / Lepkowski, William; Ghajar, M. Reza; Wilk, Seth J.; Summers, Nicholas; Thornton, Trevor; Fechner, Paul S.

In: IEEE Transactions on Electron Devices, Vol. 58, No. 6, 5765667, 06.2011, p. 1628-1634.

Research output: Contribution to journalArticle

Lepkowski, W, Ghajar, MR, Wilk, SJ, Summers, N, Thornton, T & Fechner, PS 2011, 'Scaling SOI MESFETs to 150-nm CMOS technologies', IEEE Transactions on Electron Devices, vol. 58, no. 6, 5765667, pp. 1628-1634. https://doi.org/10.1109/TED.2011.2125965
Lepkowski W, Ghajar MR, Wilk SJ, Summers N, Thornton T, Fechner PS. Scaling SOI MESFETs to 150-nm CMOS technologies. IEEE Transactions on Electron Devices. 2011 Jun;58(6):1628-1634. 5765667. https://doi.org/10.1109/TED.2011.2125965
Lepkowski, William ; Ghajar, M. Reza ; Wilk, Seth J. ; Summers, Nicholas ; Thornton, Trevor ; Fechner, Paul S. / Scaling SOI MESFETs to 150-nm CMOS technologies. In: IEEE Transactions on Electron Devices. 2011 ; Vol. 58, No. 6. pp. 1628-1634.
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