Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design

Scott Zuloaga, Rui Liu, Pai Yu Chen, Shimeng Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The resistive random access memory (RRAM) technology is a promising candidate for the replacement of NAND FLASH at ultra-scaled nodes. In this work, the scalability of a 2-layer RRAM cross-point array architecture is explored towards the 10 nm node. Device-circuit co-design methodologies are employed to optimize the array architecture. The impact of sneak paths, IR drop along the wire interconnect and RRAM device characteristics are investigated by HSPICE simulations and the memory array organization and partition are optimized by NVSim simulations. It is found that increasing the I-V nonlinearity of a memory cell by adding a cell selector helps maintain the write voltage margin at scaled nodes. With the scaling, the maximum sub-array size decreases due to the IR drop constraint thus the memory architecture evolves to a finer granularity. At the 10 nm node, by hiding a portion of the peripheral circuitry underneath the memory array, a 2-layer RRAM bank is projected to achieve ultra-high density ∼3.43 Gb/mm2, and can enable fast write bandwith ∼ 300 MB/s and read bandwidth ∼1 GB/s.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages193-196
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

Fingerprint

Data storage equipment
Networks (circuits)
Computer peripheral equipment
Memory architecture
Scalability
Wire
Bandwidth
Electric potential

Keywords

  • cross-point array
  • memory architecture
  • ReRAM
  • resistive memory
  • RRAM
  • scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Zuloaga, S., Liu, R., Chen, P. Y., & Yu, S. (2015). Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 193-196). [7168603] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168603

Scaling 2-layer RRAM cross-point array towards 10 nm node : A device-circuit co-design. / Zuloaga, Scott; Liu, Rui; Chen, Pai Yu; Yu, Shimeng.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 193-196 7168603.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zuloaga, S, Liu, R, Chen, PY & Yu, S 2015, Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7168603, Institute of Electrical and Electronics Engineers Inc., pp. 193-196, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7168603
Zuloaga S, Liu R, Chen PY, Yu S. Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July. Institute of Electrical and Electronics Engineers Inc. 2015. p. 193-196. 7168603 https://doi.org/10.1109/ISCAS.2015.7168603
Zuloaga, Scott ; Liu, Rui ; Chen, Pai Yu ; Yu, Shimeng. / Scaling 2-layer RRAM cross-point array towards 10 nm node : A device-circuit co-design. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. pp. 193-196
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