Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs

F. Ren, W. Xu, D. Marković

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

Original languageEnglish (US)
Pages (from-to)1440-1441
Number of pages2
JournalElectronics Letters
Volume49
Issue number23
DOIs
StatePublished - Nov 7 2013
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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