Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs

Fengbo Ren, W. Xu, D. Marković

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

Original languageEnglish (US)
Pages (from-to)1440-1441
Number of pages2
JournalElectronics Letters
Volume49
Issue number23
DOIs
StatePublished - Nov 7 2013
Externally publishedYes

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VLSI circuits
Field programmable gate arrays (FPGA)
Intellectual property
Logic devices
Throughput

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs. / Ren, Fengbo; Xu, W.; Marković, D.

In: Electronics Letters, Vol. 49, No. 23, 07.11.2013, p. 1440-1441.

Research output: Contribution to journalArticle

@article{8a832cf726e54ea284fd40dc2bb7e6e2,
title = "Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs",
abstract = "A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30{\%} higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.",
author = "Fengbo Ren and W. Xu and D. Marković",
year = "2013",
month = "11",
day = "7",
doi = "10.1049/el.2013.2978",
language = "English (US)",
volume = "49",
pages = "1440--1441",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "23",

}

TY - JOUR

T1 - Scalable and parameterised VLSI architecture for efficient sparse approximation in FPGAs and SoCs

AU - Ren, Fengbo

AU - Xu, W.

AU - Marković, D.

PY - 2013/11/7

Y1 - 2013/11/7

N2 - A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

AB - A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

UR - http://www.scopus.com/inward/record.url?scp=84888992122&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84888992122&partnerID=8YFLogxK

U2 - 10.1049/el.2013.2978

DO - 10.1049/el.2013.2978

M3 - Article

VL - 49

SP - 1440

EP - 1441

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 23

ER -