TY - JOUR
T1 - Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs
AU - Dorrance, Richard
AU - Ren, Fengbo
AU - Toriyama, Yuta
AU - Hafez, Amr Amin
AU - Yang, Chih Kong Ken
AU - Marković, Dejan
N1 - Funding Information:
Manuscript received September 16, 2011; revised December 6, 2011; accepted December 17, 2011. Date of publication January 26, 2012; date of current version March 23, 2012. This work was supported in part by the Defense Advanced Research Projects Agency Spin Torque Transfer–Random Access Memory (DARPA STT-RAM; HR0011-09-C-0114) Program. The review of this paper was arranged by Editor V. R. Rao.
PY - 2012/4
Y1 - 2012/4
N2 - We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ's critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide- semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities (< 6F 2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.
AB - We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ's critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide- semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities (< 6F 2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.
KW - Magnetic tunnel junction (MTJ)
KW - magnetoresistive random access memory (MRAM)
KW - process-voltage-temperature (PVT)
KW - spin-transfer torque (STT)
KW - spin-transfer torque random access memory (STT-RAM)
KW - variability
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U2 - 10.1109/TED.2011.2182053
DO - 10.1109/TED.2011.2182053
M3 - Article
AN - SCOPUS:84862830555
SN - 0018-9383
VL - 59
SP - 878
EP - 887
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 4
M1 - 6140952
ER -