Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs

Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin Hafez, Chih Kong Ken Yang, Dejan Marković

Research output: Contribution to journalArticle

56 Citations (Scopus)

Abstract

We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ's critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide- semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities (<6F 2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.

Original languageEnglish (US)
Article number6140952
Pages (from-to)878-887
Number of pages10
JournalIEEE Transactions on Electron Devices
Volume59
Issue number4
DOIs
StatePublished - Apr 2012
Externally publishedYes

Fingerprint

Scalability
Tunnel junctions
Torque
Data storage equipment
Transistors
Metals
Current density
Specifications

Keywords

  • Magnetic tunnel junction (MTJ)
  • magnetoresistive random access memory (MRAM)
  • process-voltage-temperature (PVT)
  • spin-transfer torque (STT)
  • spin-transfer torque random access memory (STT-RAM)
  • variability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Dorrance, R., Ren, F., Toriyama, Y., Hafez, A. A., Yang, C. K. K., & Marković, D. (2012). Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs. IEEE Transactions on Electron Devices, 59(4), 878-887. [6140952]. https://doi.org/10.1109/TED.2011.2182053

Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs. / Dorrance, Richard; Ren, Fengbo; Toriyama, Yuta; Hafez, Amr Amin; Yang, Chih Kong Ken; Marković, Dejan.

In: IEEE Transactions on Electron Devices, Vol. 59, No. 4, 6140952, 04.2012, p. 878-887.

Research output: Contribution to journalArticle

Dorrance, R, Ren, F, Toriyama, Y, Hafez, AA, Yang, CKK & Marković, D 2012, 'Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs', IEEE Transactions on Electron Devices, vol. 59, no. 4, 6140952, pp. 878-887. https://doi.org/10.1109/TED.2011.2182053
Dorrance, Richard ; Ren, Fengbo ; Toriyama, Yuta ; Hafez, Amr Amin ; Yang, Chih Kong Ken ; Marković, Dejan. / Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs. In: IEEE Transactions on Electron Devices. 2012 ; Vol. 59, No. 4. pp. 878-887.
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