Scalability and design-space analysis of a 1T-1MTJ memory cell

Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin, C. K. Ken Yang, Dejan Marković

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

Original languageEnglish (US)
Title of host publicationProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Pages32-36
Number of pages5
DOIs
StatePublished - 2011
Externally publishedYes
Event2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 - San Diego, CA, United States
Duration: Jun 8 2011Jun 9 2011

Other

Other2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
CountryUnited States
CitySan Diego, CA
Period6/8/116/9/11

Fingerprint

Scalability
Data storage equipment
Transistors
Current density
Specifications

Keywords

  • Design Space
  • Magnetic Tunnel Junction
  • STT-RAM
  • Variability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Dorrance, R., Ren, F., Toriyama, Y., Amin, A., Ken Yang, C. K., & Marković, D. (2011). Scalability and design-space analysis of a 1T-1MTJ memory cell. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 (pp. 32-36). [5941480] https://doi.org/10.1109/NANOARCH.2011.5941480

Scalability and design-space analysis of a 1T-1MTJ memory cell. / Dorrance, Richard; Ren, Fengbo; Toriyama, Yuta; Amin, Amr; Ken Yang, C. K.; Marković, Dejan.

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 32-36 5941480.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dorrance, R, Ren, F, Toriyama, Y, Amin, A, Ken Yang, CK & Marković, D 2011, Scalability and design-space analysis of a 1T-1MTJ memory cell. in Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011., 5941480, pp. 32-36, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, United States, 6/8/11. https://doi.org/10.1109/NANOARCH.2011.5941480
Dorrance R, Ren F, Toriyama Y, Amin A, Ken Yang CK, Marković D. Scalability and design-space analysis of a 1T-1MTJ memory cell. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 32-36. 5941480 https://doi.org/10.1109/NANOARCH.2011.5941480
Dorrance, Richard ; Ren, Fengbo ; Toriyama, Yuta ; Amin, Amr ; Ken Yang, C. K. ; Marković, Dejan. / Scalability and design-space analysis of a 1T-1MTJ memory cell. Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. pp. 32-36
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