Sample preparation for precise and quantitative electron holographic analysis of semiconductor devices

Myung Geun Han, Jing Li, Qianghua Xie, Peter Fejes, James Conner, Bill Taylor, Martha McCartney

Research output: Contribution to journalArticlepeer-review

18 Scopus citations

Abstract

Wedge polishing was used to prepare one-dimensional Si n-p junction and Si p-channel metal-oxide-silicon field effect transistor (pMOSFET) samples for precise and quantitative electrostatic potential analysis using off-axis electron holography. To avoid artifacts associated with ion milling, cloth polishing with 0.02-μm colloidal silica suspension was used for final thinning. Uniform thickness and no significant charging were observed by electron holography analysis for samples prepared entirely by this method. The effect of sample thickness was investigated and the minimum thickness for reliable results was found to be ∼160 nm. Below this thickness, measured phase changes were smaller than expected. For the pMOSFET sample, quantitative analysis of two-dimensional electrostatic potential distribution showed that the metallurgical gate length (separation between two extension junctions) was ∼54 nm, whereas the actual gate length was measured to be ∼70 nm by conventional transmission electron microscopy. Thus, source and drain junction encroachment under the gate was 16 nm.

Original languageEnglish (US)
Pages (from-to)295-301
Number of pages7
JournalMicroscopy and Microanalysis
Volume12
Issue number4
DOIs
StatePublished - Aug 2006

Keywords

  • Charging
  • Dopant encroachment
  • Dopant profiling
  • Electron holography
  • Electrostatic potential distribution
  • Gate length
  • Sample preparation

ASJC Scopus subject areas

  • Instrumentation

Fingerprint Dive into the research topics of 'Sample preparation for precise and quantitative electron holographic analysis of semiconductor devices'. Together they form a unique fingerprint.

Cite this