Robust ultra-low voltage ROM design

Mingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, David Blaauw

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18μm CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages423-426
Number of pages4
DOIs
StatePublished - 2008
Externally publishedYes
EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: Sep 21 2008Sep 24 2008

Other

OtherIEEE 2008 Custom Integrated Circuits Conference, CICC 2008
CountryUnited States
CitySan Jose, CA
Period9/21/089/24/08

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Seok, M., Hanson, S., Seo, J., Sylvester, D., & Blaauw, D. (2008). Robust ultra-low voltage ROM design. In Proceedings of the Custom Integrated Circuits Conference (pp. 423-426). [4672110] https://doi.org/10.1109/CICC.2008.4672110