Robust ultra-low voltage ROM design

Mingoo Seok; Scott Hanson; Jae-sun Seo; Dennis Sylvester; David Blaauw

doi:10.1109/CICC.2008.4672110

Robust ultra-low voltage ROM design

Mingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, David Blaauw

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Scopus citations

Abstract

SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18μm CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.

Original language	English (US)
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Pages	423-426
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2008.4672110
State	Published - 2008
Externally published	Yes
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: Sep 21 2008 → Sep 24 2008

Other

Other	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008
Country/Territory	United States
City	San Jose, CA
Period	9/21/08 → 9/24/08

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2008.4672110

Cite this

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title = "Robust ultra-low voltage ROM design",

abstract = "SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18μm CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.",

author = "Mingoo Seok and Scott Hanson and Jae-sun Seo and Dennis Sylvester and David Blaauw",

year = "2008",

doi = "10.1109/CICC.2008.4672110",

language = "English (US)",

pages = "423--426",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 21-09-2008 Through 24-09-2008",

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T1 - Robust ultra-low voltage ROM design

AU - Seok, Mingoo

AU - Hanson, Scott

AU - Seo, Jae-sun

AU - Sylvester, Dennis

AU - Blaauw, David

PY - 2008

Y1 - 2008

N2 - SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18μm CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.

AB - SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18μm CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.

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Robust ultra-low voltage ROM design

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