TY - GEN
T1 - Robust RRAM-based In-Memory Computing in Light of Model Stability
AU - Krishnan, Gokul
AU - Sun, Jingbo
AU - Hazra, Jubin
AU - Du, Xiaocong
AU - Liehr, Maximilian
AU - Li, Zheng
AU - Beckmann, Karsten
AU - Joshi, Rajiv V.
AU - Cady, Nathaniel C.
AU - Cao, Yu
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported in part by C-BRIC, one of the six centers in JUMP, a Semiconductor Research Corporation (SRC) program, and the Air Force Research Laboratory award #FA8750-19-1-0014.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/3
Y1 - 2021/3
N2 - Resistive random-access memory (RRAM)-based in-memory computing (IMC) architectures offer an energy-efficient solution for DNN acceleration. However, the performance of RRAM-based IMC is limited by device nonidealities, ADC precision, and algorithm properties. To address this, in this work, first, we perform statistical characterization of RRAM device variation and temporal degradation from 300mm wafers of a fully integrated CMOS/RRAM 1T1R test chip at 65nm. Through this, we build a realistic foundation to assess the robustness. Second, we develop a cross-layer simulation tool that incorporates device, circuit, architecture, and algorithm properties under a single roof for system evaluation. Finally, we propose a novel loss landscape-based DNN model selection for stability, which effectively tolerates device variations and achieves a post-mapping accuracy higher than that with 50% lower RRAM variations. We demonstrate the proposed method for different DNNs on both CIFAR-10 and CIFAR-100 datasets.
AB - Resistive random-access memory (RRAM)-based in-memory computing (IMC) architectures offer an energy-efficient solution for DNN acceleration. However, the performance of RRAM-based IMC is limited by device nonidealities, ADC precision, and algorithm properties. To address this, in this work, first, we perform statistical characterization of RRAM device variation and temporal degradation from 300mm wafers of a fully integrated CMOS/RRAM 1T1R test chip at 65nm. Through this, we build a realistic foundation to assess the robustness. Second, we develop a cross-layer simulation tool that incorporates device, circuit, architecture, and algorithm properties under a single roof for system evaluation. Finally, we propose a novel loss landscape-based DNN model selection for stability, which effectively tolerates device variations and achieves a post-mapping accuracy higher than that with 50% lower RRAM variations. We demonstrate the proposed method for different DNNs on both CIFAR-10 and CIFAR-100 datasets.
KW - Deep Neural Network
KW - In-Memory Computing
KW - Model Stability
KW - RRAM
KW - Robustness
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U2 - 10.1109/IRPS46558.2021.9405092
DO - 10.1109/IRPS46558.2021.9405092
M3 - Conference contribution
AN - SCOPUS:85105585409
T3 - IEEE International Reliability Physics Symposium Proceedings
BT - 2021 IEEE International Reliability Physics Symposium, IRPS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE International Reliability Physics Symposium, IRPS 2021
Y2 - 21 March 2021 through 24 March 2021
ER -