Resistive random-access memory (RRAM)-based in-memory computing (IMC) architectures offer an energy-efficient solution for DNN acceleration. However, the performance of RRAM-based IMC is limited by device nonidealities, ADC precision, and algorithm properties. To address this, in this work, first, we perform statistical characterization of RRAM device variation and temporal degradation from 300mm wafers of a fully integrated CMOS/RRAM 1T1R test chip at 65nm. Through this, we build a realistic foundation to assess the robustness. Second, we develop a cross-layer simulation tool that incorporates device, circuit, architecture, and algorithm properties under a single roof for system evaluation. Finally, we propose a novel loss landscape-based DNN model selection for stability, which effectively tolerates device variations and achieves a post-mapping accuracy higher than that with 50% lower RRAM variations. We demonstrate the proposed method for different DNNs on both CIFAR-10 and CIFAR-100 datasets.