Robust design of high fan-in/out subthreshold circuits

Jinhui Chen, Lawrence T. Clark, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Operating CMOS circuits with power supplies below the threshold voltage has been suggested for ultra-low power systems. High fan-in or fan-out circuits, such as those in memories, are prone to failure when operating in this regime. Vanishing noise margins due to reduced transistor on-to-off current ratios result in circuit failure as the supply voltage shrinks. Therefore, design guidelines for robust subthreshold logic circuit are developed in this paper. First, an analytical model is derived to determine a circuit's fan-in/out limitations and the minimum supply voltage for robust subthreshold operation. Excellent agreement between the analytical model and circuit simulations is shown. This model is applied to the analysis of circuit robustness as affected by design choices, both systematic and random processing variations, supply voltage fluctuations, and temperature variations.

Original languageEnglish (US)
Title of host publicationProceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors, ICCD 2005
Pages405-410
Number of pages6
DOIs
StatePublished - 2005
Event2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States
Duration: Oct 2 2005Oct 5 2005

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume2005
ISSN (Print)1063-6404

Other

Other2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Country/TerritoryUnited States
CitySan Jose, CA
Period10/2/0510/5/05

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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