TY - GEN
T1 - Rigorous extraction of process variations for 65nm CMOS design
AU - Zhao, Wei
AU - Cao, Yu
AU - Liu, Frank
AU - Agarwal, Kanak
AU - Acharyya, Dhruva
AU - Nassif, Sani
AU - Nowka, Kevin
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2007
Y1 - 2007
N2 - Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, we present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65nm SOI process. We recognize gate length (L), threshold voltage (Vth) and mobility (μ) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and Vth variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.
AB - Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, we present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65nm SOI process. We recognize gate length (L), threshold voltage (Vth) and mobility (μ) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and Vth variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.
UR - http://www.scopus.com/inward/record.url?scp=37549006162&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=37549006162&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2007.4430253
DO - 10.1109/ESSCIRC.2007.4430253
M3 - Conference contribution
AN - SCOPUS:37549006162
SN - 1424411254
SN - 9781424411252
T3 - ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
SP - 89
EP - 92
BT - ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
T2 - ESSCIRC 2007 - 33rd European Solid-State Circuits Conference
Y2 - 11 September 2007 through 13 September 2007
ER -