Reverse-body biasing for radiation-hard by design logic gates

Lawrence T. Clark, Karl C. Mohr, Keith Holbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Different radiation hardening by design techniques for mitigating total ionizing dose (TID) effects in NMOS transistors are presented. NMOS annular layout transistors are compared to two-edge and hardened by reverse-body bias (RBB) with respect to CMOS gate area, delay, active and leakage power, and TID hardness. Accelerated testing using Co-60 irradiation of test structures on a 130 nm bulk CMOS process shows that RBB provides smaller devices and allows less chip-level leakage at 1 Mrad(Si) than a design hardened using annular gates has pre-irradiation. Simulations of fanout-of-four (F04) two-input NAND gates show that RBB provides an energy-delay product (EDP) comparable to conventional two-edge gates. Different annular topologies have EDP 35% to over 350% greater.

Original languageEnglish (US)
Title of host publication2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
Pages582-583
Number of pages2
DOIs
StatePublished - Sep 25 2007
Event45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
Duration: Apr 15 2007Apr 19 2007

Publication series

NameAnnual Proceedings - Reliability Physics (Symposium)
ISSN (Print)0099-9512

Other

Other45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
Country/TerritoryUnited States
CityPhoenix, AZ
Period4/15/074/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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