Return data interleaving for multi-channel embedded CMPs systems

Fei Hong, Aviral Shrivastava, Jongeun Lee

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

Using multi-channel memory subsystems is an efficient way of satisfying high volume memory requests from CMPs. At the same time, the imbalance between memory bandwidth and bus performance opens up new possibility of optimization before they are sent to bus. This paper presents a new memory controller design for embedded CMPs systems when the return data from the return buffer is sent back to bus. Our scheduling policy, called return data interleaving (RDI) interleaves the return data of each request in a round robin manner. Further, for each request, it sends the critical word first. To evaluate our technique, we model an Intel XScale-based CMPs using M5 simulator for CMPs simulation and DRAMsim for memory subsystem simulation and examine the performance of MiBench and SPEC2000 benchmarks. Simulation results show that for memory-bound benchmarks running on the CMPs systems with the number of cores from 6 to 16, RDI can improve the execution time by average 11% and up to 16.9%.

Original languageEnglish (US)
Article number5936661
Pages (from-to)1351-1354
Number of pages4
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number7
DOIs
StatePublished - Jan 1 2012

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Keywords

  • Chip multi-core processor
  • multi-channel memory
  • return data interleaving (RDI)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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