Retargetable pipeline hazard detection for partially bypassed processors

Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alex Nicolau

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

Register bypassing is a widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, it has significant impact on the cycle time, area, and power consumption of the processor. Owing to the strict design constraints on the performance, cost, and the power consumption of embedded processor systems, architects seek a compromise between the design parameters by implementing partial bypassing in processors. However, partial bypassing in processors presents challenges for compilation. Traditional data hazard detection and/or avoidance techniques used in retargetable compilers that assume a constant value of operation latency, break down in the presence of partial bypassing. In this article, we present the concept of operation tables (OTs) that can be used to accurately detect data hazards, even in the presence of incomplete bypassing. OTs integrate the detection of all kinds of pipeline hazards in a unified framework, and can, therefore, be easily deployed in a compiler to generate better schedules. Our experimental results on the popular Intel XScale embedded processor running embedded applications from the MiBench suite, demonstrate that accurate pipeline hazard detection by OTs can result in up to 20% performance improvement over the best performing GCC generated code. Finally, we demonstrate the usefulness of OTs over various bypass configurations of the Intel XScale.

Original languageEnglish (US)
Article number1664901
Pages (from-to)791-801
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume14
Issue number8
DOIs
StatePublished - Aug 1 2006

Keywords

  • Bypasses
  • Forwarding path
  • Operation table
  • Partial bypassing
  • Partially bypassed processor
  • Pipeline hazard detection
  • Processor pipeline

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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