Remote plasma enhanced chemical vapor deposition SiO2 in silicon based nanostructures

D. K. Ferry

Research output: Contribution to journalArticle

Abstract

In the depletion gate approach to silicon-based nanostructures, a deposited oxide covering tiny metallic or suicide gate structures must function as a metal-oxide-semiconductor field effect transistor gate oxide. Depending upon the implementation, it may form the Si/SiO2 interface or be placed upon a very thin thermal oxide. In the former case, bonding between the silicon and SiO2 must be nearly perfect in order to achieve the high mobility required for observing quantum effects. In the latter case, the deposited oxide must not allow leakage current to obscure effects being observed, nor degrade the previously established thermal interface during deposition. Remote plasma enhanced chemical vapor deposited (RPECVD) silicon dioxide has been studied for use in silicon-based nanostructures. For thin oxides deposited at low temperature, oxide surface roughness has been shown to perturb the potential landscape seen by an electron traveling in a silicon inversion layer. [M. J. Rack, D. Vasileska, D. K. Ferry, and M. Siderov, J. Vac. Sci. Technol. B 16, 2165 (1998).] We have further explored processing parameters that influence the deposited oxide surface roughness, presumably roughened primarily by gas phase nucleation, and examined the correlation between roughness and oxide reliability. We found that processing conditions that reduce the oxide roughness and unwanted oxidation of the depletion gate structures are not necessarily those that produce the best silicon/oxide interfaces, nor the most defect-free bulk oxides in our RPECVD system. Specific processes tailored for particular device strategies are presented. The low temperature process at 175°C is extensively explored.

Original languageEnglish (US)
Pages (from-to)1840-1847
Number of pages8
JournalJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Volume17
Issue number4
StatePublished - 1999

Fingerprint

Plasma enhanced chemical vapor deposition
Nanostructures
vapor deposition
Silicon
Oxides
oxides
silicon
Surface roughness
surface roughness
depletion
roughness
Vapors
vapors
Gates (transistor)
Plasmas
Inversion layers
Silicon oxides
MOSFET devices
Processing
silicon oxides

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)
  • Surfaces and Interfaces

Cite this

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abstract = "In the depletion gate approach to silicon-based nanostructures, a deposited oxide covering tiny metallic or suicide gate structures must function as a metal-oxide-semiconductor field effect transistor gate oxide. Depending upon the implementation, it may form the Si/SiO2 interface or be placed upon a very thin thermal oxide. In the former case, bonding between the silicon and SiO2 must be nearly perfect in order to achieve the high mobility required for observing quantum effects. In the latter case, the deposited oxide must not allow leakage current to obscure effects being observed, nor degrade the previously established thermal interface during deposition. Remote plasma enhanced chemical vapor deposited (RPECVD) silicon dioxide has been studied for use in silicon-based nanostructures. For thin oxides deposited at low temperature, oxide surface roughness has been shown to perturb the potential landscape seen by an electron traveling in a silicon inversion layer. [M. J. Rack, D. Vasileska, D. K. Ferry, and M. Siderov, J. Vac. Sci. Technol. B 16, 2165 (1998).] We have further explored processing parameters that influence the deposited oxide surface roughness, presumably roughened primarily by gas phase nucleation, and examined the correlation between roughness and oxide reliability. We found that processing conditions that reduce the oxide roughness and unwanted oxidation of the depletion gate structures are not necessarily those that produce the best silicon/oxide interfaces, nor the most defect-free bulk oxides in our RPECVD system. Specific processes tailored for particular device strategies are presented. The low temperature process at 175°C is extensively explored.",
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