To mitigate the significant main memory access latency in modern chip multiprocessors, multi-level on-chip caches are used to bridge the gap by retaining frequently used data closer to the processor cores. Such dependence on the last-level cache (LLC) has motivated numerous innovations in cache management schemes. However, most prior works focus their efforts on optimizing cache miss counts experienced by applications, irrespective of the interactions between the LLC and other components in the memory hierarchy such as the main memory. This results in sub-optimal performance improvements, since reducing miss rates does not directly translate to increased IPC performance. In this paper, we show that in addition to the recency information provided by the cache replacement policy, post eviction reuse distance (PERD) and main memory access latency cost are useful to make better-informed eviction decisions at the LLC. We propose ReMAP, Reuse and Memory Access Cost aware eviction policy, that takes reuse characteristics and memory access behavior into consideration when making eviction decisions. ReMAP achieves higher performance compared to prior works. Our full-system simulation results show that ReMAP reduces the number of misses of SPEC2006 applications by as much as 13% over the baseline LRU replacement and by an average of 6.5% while MLP-aware replacement and DRRIP reduce the miss counts by -0.7% and 5% respectively. More importantly, ReMAP achieves an average of 4.6% IPC performance gain across the SPEC2006 applications while MLP-aware replacement and DRRIP see only 1.8% and 2.3% respectively.