Abstract
The transition metal oxide (TMO) resistive random access memory (ReRAM) has been identified as one of the most promising candidates for the next generation non-volatile memory (NVM) technology. Numerous TMO ReRAMs with different materials have been developed and demonstrate attractive characteristics, such as fast read/write speed, low power consumption, high integrated density, and good scalability. Among them, the most attractive characteristic of ReRAM is its cross-point structure which features a 4F2 cell size. However, the existence of sneak current and voltage drop along the wire resistance in a cross-point array brings in extra design challenges. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this paper, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure modes on the reliability of cross-point array. We also propose an error resilient architecture which avoids unnecessary writes in the hard error detection unit. Experimental results show that our design can extend the lifetime of ReRAM up to 75% over the design without hard error detections and up to 12% over the design with "write-verify" detection mechanism.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
| Publisher | Association for Computing Machinery |
| Pages | 145-150 |
| Number of pages | 6 |
| ISBN (Print) | 9781450328166 |
| DOIs | |
| State | Published - 2014 |
| Event | 24th Great Lakes Symposium on VLSI, GLSVLSI 2014 - Houston, TX, United States Duration: May 21 2014 → May 23 2014 |
Other
| Other | 24th Great Lakes Symposium on VLSI, GLSVLSI 2014 |
|---|---|
| Country | United States |
| City | Houston, TX |
| Period | 5/21/14 → 5/23/14 |
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Keywords
- cross-point
- reliability
- ReRAM
ASJC Scopus subject areas
- Engineering(all)
Cite this
Reliability-aware cross-point resistive memory design. / Xu, Cong; Niu, Dimin; Zheng, Yang; Yu, Shimeng; Xie, Yuan.
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Association for Computing Machinery, 2014. p. 145-150.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Reliability-aware cross-point resistive memory design
AU - Xu, Cong
AU - Niu, Dimin
AU - Zheng, Yang
AU - Yu, Shimeng
AU - Xie, Yuan
PY - 2014
Y1 - 2014
N2 - The transition metal oxide (TMO) resistive random access memory (ReRAM) has been identified as one of the most promising candidates for the next generation non-volatile memory (NVM) technology. Numerous TMO ReRAMs with different materials have been developed and demonstrate attractive characteristics, such as fast read/write speed, low power consumption, high integrated density, and good scalability. Among them, the most attractive characteristic of ReRAM is its cross-point structure which features a 4F2 cell size. However, the existence of sneak current and voltage drop along the wire resistance in a cross-point array brings in extra design challenges. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this paper, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure modes on the reliability of cross-point array. We also propose an error resilient architecture which avoids unnecessary writes in the hard error detection unit. Experimental results show that our design can extend the lifetime of ReRAM up to 75% over the design without hard error detections and up to 12% over the design with "write-verify" detection mechanism.
AB - The transition metal oxide (TMO) resistive random access memory (ReRAM) has been identified as one of the most promising candidates for the next generation non-volatile memory (NVM) technology. Numerous TMO ReRAMs with different materials have been developed and demonstrate attractive characteristics, such as fast read/write speed, low power consumption, high integrated density, and good scalability. Among them, the most attractive characteristic of ReRAM is its cross-point structure which features a 4F2 cell size. However, the existence of sneak current and voltage drop along the wire resistance in a cross-point array brings in extra design challenges. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this paper, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure modes on the reliability of cross-point array. We also propose an error resilient architecture which avoids unnecessary writes in the hard error detection unit. Experimental results show that our design can extend the lifetime of ReRAM up to 75% over the design without hard error detections and up to 12% over the design with "write-verify" detection mechanism.
KW - cross-point
KW - reliability
KW - ReRAM
UR - http://www.scopus.com/inward/record.url?scp=84902583679&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84902583679&partnerID=8YFLogxK
U2 - 10.1145/2591513.2591528
DO - 10.1145/2591513.2591528
M3 - Conference contribution
AN - SCOPUS:84902583679
SN - 9781450328166
SP - 145
EP - 150
BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
PB - Association for Computing Machinery
ER -