Reliability-aware cross-point resistive memory design

Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The transition metal oxide (TMO) resistive random access memory (ReRAM) has been identified as one of the most promising candidates for the next generation non-volatile memory (NVM) technology. Numerous TMO ReRAMs with different materials have been developed and demonstrate attractive characteristics, such as fast read/write speed, low power consumption, high integrated density, and good scalability. Among them, the most attractive characteristic of ReRAM is its cross-point structure which features a 4F2 cell size. However, the existence of sneak current and voltage drop along the wire resistance in a cross-point array brings in extra design challenges. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this paper, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure modes on the reliability of cross-point array. We also propose an error resilient architecture which avoids unnecessary writes in the hard error detection unit. Experimental results show that our design can extend the lifetime of ReRAM up to 75% over the design without hard error detections and up to 12% over the design with "write-verify" detection mechanism.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
PublisherAssociation for Computing Machinery
Pages145-150
Number of pages6
ISBN (Print)9781450328166
DOIs
StatePublished - 2014
Event24th Great Lakes Symposium on VLSI, GLSVLSI 2014 - Houston, TX, United States
Duration: May 21 2014May 23 2014

Other

Other24th Great Lakes Symposium on VLSI, GLSVLSI 2014
CountryUnited States
CityHouston, TX
Period5/21/145/23/14

Fingerprint

Data storage equipment
Error detection
Transition metals
Oxides
Failure modes
Scalability
Electric power utilization
Wire

Keywords

  • cross-point
  • reliability
  • ReRAM

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Xu, C., Niu, D., Zheng, Y., Yu, S., & Xie, Y. (2014). Reliability-aware cross-point resistive memory design. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 145-150). Association for Computing Machinery. https://doi.org/10.1145/2591513.2591528

Reliability-aware cross-point resistive memory design. / Xu, Cong; Niu, Dimin; Zheng, Yang; Yu, Shimeng; Xie, Yuan.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Association for Computing Machinery, 2014. p. 145-150.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Xu, C, Niu, D, Zheng, Y, Yu, S & Xie, Y 2014, Reliability-aware cross-point resistive memory design. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Association for Computing Machinery, pp. 145-150, 24th Great Lakes Symposium on VLSI, GLSVLSI 2014, Houston, TX, United States, 5/21/14. https://doi.org/10.1145/2591513.2591528
Xu C, Niu D, Zheng Y, Yu S, Xie Y. Reliability-aware cross-point resistive memory design. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Association for Computing Machinery. 2014. p. 145-150 https://doi.org/10.1145/2591513.2591528
Xu, Cong ; Niu, Dimin ; Zheng, Yang ; Yu, Shimeng ; Xie, Yuan. / Reliability-aware cross-point resistive memory design. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Association for Computing Machinery, 2014. pp. 145-150
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