Register file power reduction using bypass sensitive compiler

Sanghyun Park; Aviral Shrivastava; Nikil Dutt; Alex Nicolau; Yunheung Paek; Eugene Earlie

doi:10.1109/TCAD.2008.923254

Register file power reduction using bypass sensitive compiler

Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Yunheung Paek, Eugene Earlie

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed "on-demand register fetch read" architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.

Original language	English (US)
Article number	4526748
Pages (from-to)	1155-1159
Number of pages	5
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	27
Issue number	6
DOIs	https://doi.org/10.1109/TCAD.2008.923254
State	Published - Jun 2008

Keywords

Bypass sensitive
Compiler
Forwarding paths
Operation table
Power consumption
Register file

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2008.923254

Cite this

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title = "Register file power reduction using bypass sensitive compiler",

abstract = "This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed {"}on-demand register fetch read{"} architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.",

keywords = "Bypass sensitive, Compiler, Forwarding paths, Operation table, Power consumption, Register file",

author = "Sanghyun Park and Aviral Shrivastava and Nikil Dutt and Alex Nicolau and Yunheung Paek and Eugene Earlie",

note = "Funding Information: Manuscript received July 28, 2007; revised November 19, 2007. This work is supported in part by a grant from Microsoft, by IDEC, by the Ministry of Information and Communication (MIC), Korea, under the Information Technology Research Center (ITRC) support program supervised by the Institute of Information Technology Assessment (IITA), which is the IT R&D program of MIC/IITA [2006-S-006-01, Components/Module Technology for Ubiquitous Terminals], under Grant IITA-2006-C1090-0603-0020, by the Human Resource Development Project for IT SoC Architect, and by the Nano IP/SoC promotion group of the Seoul R&BD Program in 2007. This paper was recommended by Associate Editor L. Benini.",

year = "2008",

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doi = "10.1109/TCAD.2008.923254",

language = "English (US)",

volume = "27",

pages = "1155--1159",

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AU - Park, Sanghyun

AU - Shrivastava, Aviral

AU - Dutt, Nikil

AU - Nicolau, Alex

AU - Paek, Yunheung

AU - Earlie, Eugene

N1 - Funding Information: Manuscript received July 28, 2007; revised November 19, 2007. This work is supported in part by a grant from Microsoft, by IDEC, by the Ministry of Information and Communication (MIC), Korea, under the Information Technology Research Center (ITRC) support program supervised by the Institute of Information Technology Assessment (IITA), which is the IT R&D program of MIC/IITA [2006-S-006-01, Components/Module Technology for Ubiquitous Terminals], under Grant IITA-2006-C1090-0603-0020, by the Human Resource Development Project for IT SoC Architect, and by the Nano IP/SoC promotion group of the Seoul R&BD Program in 2007. This paper was recommended by Associate Editor L. Benini.

PY - 2008/6

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N2 - This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed "on-demand register fetch read" architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.

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KW - Bypass sensitive

KW - Compiler

KW - Forwarding paths

KW - Operation table

KW - Power consumption

KW - Register file

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Register file power reduction using bypass sensitive compiler

Abstract

Keywords

ASJC Scopus subject areas

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