Register file power reduction using bypass sensitive compiler

Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Yunheung Paek, Eugene Earlie

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed "on-demand register fetch read" architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.

Original languageEnglish (US)
Article number4526748
Pages (from-to)1155-1159
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number6
DOIs
StatePublished - Jun 2008

Keywords

  • Bypass sensitive
  • Compiler
  • Forwarding paths
  • Operation table
  • Power consumption
  • Register file

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

Register file power reduction using bypass sensitive compiler. / Park, Sanghyun; Shrivastava, Aviral; Dutt, Nikil; Nicolau, Alex; Paek, Yunheung; Earlie, Eugene.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 6, 4526748, 06.2008, p. 1155-1159.

Research output: Contribution to journalArticle

Park, Sanghyun ; Shrivastava, Aviral ; Dutt, Nikil ; Nicolau, Alex ; Paek, Yunheung ; Earlie, Eugene. / Register file power reduction using bypass sensitive compiler. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2008 ; Vol. 27, No. 6. pp. 1155-1159.
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