Reference calibration of body-voltage sensing circuit for high-speed STT-RAMs

Fengbo Ren, Henry Park, Chih Kong Ken Yang, Dejan Markoviæ

Research output: Contribution to journalArticle

18 Scopus citations

Abstract

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-bit reference calibration can improve the worst-case read margin in a 1-Mb memory by over 3 times. This leads to up to 30% higher yield across all process corners. In order to maintain the yield improvement even in the worst-case corner, independent calibration circuitry has to be deployed for each memory array.

Original languageEnglish (US)
Pages (from-to)2932-2939
Number of pages8
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number11
DOIs
StatePublished - Apr 5 2013
Externally publishedYes

Keywords

  • Body-voltage sensing
  • CMOS
  • Magnetic tunnel junction (MTJ)
  • Nonvolatile memory
  • Read margin
  • Reference calibration
  • Sensing margin
  • Spin-transfer torque random access memory (STT-RAM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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