Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation

Aditya Gujja, Srivatsan Chellappa, Chandarasekaran Ramamurthy, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both SEU and SET with reduced power consumption. The approach utilizes commercial CAD tools. An advanced encryption system is implemented with the proposed design is compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation by 18% over an improved version of the prior approach, with negligible area impact.

Original languageEnglish (US)
Title of host publication2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-December
ISBN (Electronic)9781509002313
DOIs
StatePublished - Dec 24 2015
Externally publishedYes
Event15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 - Moscow, Russian Federation
Duration: Sep 14 2015Sep 18 2015

Other

Other15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015
CountryRussian Federation
CityMoscow
Period9/14/159/18/15

Fingerprint

latches
clocks
Clocks
computer aided design
pulses
Cryptography
Computer aided design
Computer systems
Electric power utilization
methodology
synthesis
energy

Keywords

  • Flip-Flop
  • Multiple node charge collection
  • Single event transient
  • Single event upset
  • Temporal hardening
  • Triple mode redundancy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Radiation

Cite this

Gujja, A., Chellappa, S., Ramamurthy, C., & Clark, L. T. (2015). Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation. In 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015 (Vol. 2015-December). [7365658] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RADECS.2015.7365658

Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation. / Gujja, Aditya; Chellappa, Srivatsan; Ramamurthy, Chandarasekaran; Clark, Lawrence T.

2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. Vol. 2015-December Institute of Electrical and Electronics Engineers Inc., 2015. 7365658.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gujja, A, Chellappa, S, Ramamurthy, C & Clark, LT 2015, Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation. in 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. vol. 2015-December, 7365658, Institute of Electrical and Electronics Engineers Inc., 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015, Moscow, Russian Federation, 9/14/15. https://doi.org/10.1109/RADECS.2015.7365658
Gujja A, Chellappa S, Ramamurthy C, Clark LT. Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation. In 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. Vol. 2015-December. Institute of Electrical and Electronics Engineers Inc. 2015. 7365658 https://doi.org/10.1109/RADECS.2015.7365658
Gujja, Aditya ; Chellappa, Srivatsan ; Ramamurthy, Chandarasekaran ; Clark, Lawrence T. / Redundant skewed clocking of pulse-clocked latches for low power soft error mitigation. 2015 15th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2015. Vol. 2015-December Institute of Electrical and Electronics Engineers Inc., 2015.
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