Reducing transistor variability for high performance low power chips

Robert Rogenmoser, Lawrence T. Clark

Research output: Contribution to journalArticle

12 Scopus citations

Abstract

CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.

Original languageEnglish (US)
Article number6461870
Pages (from-to)18-26
Number of pages9
JournalIEEE Micro
Volume33
Issue number2
DOIs
StatePublished - Apr 16 2013

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Keywords

  • CMOS
  • DDC
  • VLSI
  • body bias
  • deeply depleted channel transistor
  • low power
  • undoped channel transistor
  • voltage scaling

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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