Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching

Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components-including registers, functional units, and L1I and L1D cache frames-without slowing the clock frequency or pessimistically assuming that all components are slow. Using ideas previously developed for other purposes-criticality-based allocation of resources, prefetching, and prefetch buffering-we allow design engineers to aggressively set the clock frequency without worrying about the subset of components that cannot meet this frequency. Our techniques outperform speed binning, because clock frequency benefits outweigh slight losses in IPC.

Original languageEnglish (US)
Title of host publicationConference on Computing Frontiers - Proceedings of the 2008 Conference on Computing Frontiers, CF'08
Pages129-138
Number of pages10
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 Conference on Computing Frontiers, CF'08 - Ischia, Italy
Duration: May 5 2008May 7 2008

Publication series

NameConference on Computing Frontiers - Proceedings of the 2008 Conference on Computing Frontiers, CF'08

Conference

Conference2008 Conference on Computing Frontiers, CF'08
Country/TerritoryItaly
CityIschia
Period5/5/085/7/08

Keywords

  • Microarchitecture
  • Process variability

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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