TY - JOUR
T1 - Reducing SRAM Reading Power with Column Data Segment and Weights Correlation Enhancement for CNN Processing
AU - Xu, Han
AU - Li, Ziwei
AU - Li, Ziru
AU - Fan, Deliang
AU - Qiao, Fei
AU - Wei, Qi
AU - Luo, Li
AU - Liu, Xinjun
AU - Yang, Huazhong
N1 - Funding Information:
This work was supported by National Key Research and Development Program of China under Grant 2018YFB1702500, and in part by Beijing Innovation Center for Future Chips, Tsinghua University.
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2021/11/1
Y1 - 2021/11/1
N2 - Convolutional neural network (CNN) has been widely deployed in various processors for intelligent visual signal processing. However, the large amount of activations and weights in CNN causes huge power consumption on SRAM access. Data-adaptive SRAM design is a widely studied method to reduce SRAM reading power based on the utilization of data patterns, while current designs only exploit data patterns in a coarse granularity, and have no advantages when faced with randomly distributed weight data. In this article, we propose a hardware-software co-design scheme to reduce SRAM reading power for CNN processing. First, we propose a reconfigurable data-adaptive SRAM architecture with column data segmentation (CDS-RSRAM) to utilize data patterns. Data in one column is partitioned into several segments, and finer-grained data patterns are exploited within each segment for further reading power reduction. Then, a novel training method - minimum segmented neighbor difference (miniSND) - is proposed for enhancing the correlation of weights. MiniSND improves the similarity of weights without classification accuracy degradation, thus weights could benefit from CDS-RSRAM and be read out with less power consumption. Simulation results demonstrate that the co-design scheme saves up to 66%(8b)/89%(2b) power consumption compared with 8T SRAM.
AB - Convolutional neural network (CNN) has been widely deployed in various processors for intelligent visual signal processing. However, the large amount of activations and weights in CNN causes huge power consumption on SRAM access. Data-adaptive SRAM design is a widely studied method to reduce SRAM reading power based on the utilization of data patterns, while current designs only exploit data patterns in a coarse granularity, and have no advantages when faced with randomly distributed weight data. In this article, we propose a hardware-software co-design scheme to reduce SRAM reading power for CNN processing. First, we propose a reconfigurable data-adaptive SRAM architecture with column data segmentation (CDS-RSRAM) to utilize data patterns. Data in one column is partitioned into several segments, and finer-grained data patterns are exploited within each segment for further reading power reduction. Then, a novel training method - minimum segmented neighbor difference (miniSND) - is proposed for enhancing the correlation of weights. MiniSND improves the similarity of weights without classification accuracy degradation, thus weights could benefit from CDS-RSRAM and be read out with less power consumption. Simulation results demonstrate that the co-design scheme saves up to 66%(8b)/89%(2b) power consumption compared with 8T SRAM.
KW - Convolutional neural network (CNN) processor
KW - SRAM
KW - correlation enhancement
KW - data patterns
KW - low power
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U2 - 10.1109/TCAD.2020.3041380
DO - 10.1109/TCAD.2020.3041380
M3 - Article
AN - SCOPUS:85097369284
VL - 40
SP - 2237
EP - 2250
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 11
ER -