The read access delay of a static random access memory (SRAM) is dominated by the time required to develop a voltage differential on the bit-lines, particularly for small, fast level-1 (L1) caches in microprocessors. For a robust design, the bit-lines must develop a differential sufficient to overcome mismatch due to sense amplifier offsets and other signal path components before the data is sensed. This must be accomplished across all process skews and voltages. This paper proposes a design and optimization technique to minimize the bit-line voltage differential variation across process corners and voltages, which increases the read frequency by reducing the delay guard-band required at the design process corner. The technique reduces the required timing guard-band by minimizing the effects of process variation on the circuit delays. On a 90 nm high-performance cache memory data array, the typical corner guard-band required to generate the differential is reduced by 78%. Total variation in bit-line differential is reduced from 243 to 45 mV across process and voltage corners.
- CMOS memory integrated circuits
- Memory architecture
- Programmable timers
- Replica timing
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering