Abstract
In this paper, we propose a processor which is optimized for idle mode operation of a software defined radio (SDR.) terminal. Since a SDR terminal spends most of its time in the idle mode, reducing the power consumption in this mode directly translates to longer terminal standby time. Workload analysis of idle mode operations of contemporary standards showed that these are dominated by FIR filtering, which can be easily parallelized. This analysis was used in the design of the idle mode processor. The key architectural components are an SIMD unit for the parallel computations that dominate the workload, a conventional scalar unit for the sequential computations, and a control unit which supports efficient data memory access and loop control. The idle mode processor was modeled with Verilog and synthesized using standard cells in 0.13 micron technology. It consumes about 9mW at 1.08V.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the International Symposium on Low Power Electronics and Design |
| Pages | 101-106 |
| Number of pages | 6 |
| Volume | 2006 |
| DOIs | |
| State | Published - 2006 |
| Event | ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany Duration: Oct 4 2006 → Oct 6 2006 |
Other
| Other | ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design |
|---|---|
| Country | Germany |
| City | Tegernsee, Bavaria |
| Period | 10/4/06 → 10/6/06 |
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Keywords
- Baseband processor
- Idle mode
- Low power
- SDR
- SIMD
- Software defined radio
- Wireless terminal
ASJC Scopus subject areas
- Engineering(all)
Cite this
Reducing idle mode power in software defined radio terminals. / LEE, Hyunseok; Mudge, Trevor; Chakrabarti, Chaitali.
Proceedings of the International Symposium on Low Power Electronics and Design. Vol. 2006 2006. p. 101-106.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Reducing idle mode power in software defined radio terminals
AU - LEE, Hyunseok
AU - Mudge, Trevor
AU - Chakrabarti, Chaitali
PY - 2006
Y1 - 2006
N2 - In this paper, we propose a processor which is optimized for idle mode operation of a software defined radio (SDR.) terminal. Since a SDR terminal spends most of its time in the idle mode, reducing the power consumption in this mode directly translates to longer terminal standby time. Workload analysis of idle mode operations of contemporary standards showed that these are dominated by FIR filtering, which can be easily parallelized. This analysis was used in the design of the idle mode processor. The key architectural components are an SIMD unit for the parallel computations that dominate the workload, a conventional scalar unit for the sequential computations, and a control unit which supports efficient data memory access and loop control. The idle mode processor was modeled with Verilog and synthesized using standard cells in 0.13 micron technology. It consumes about 9mW at 1.08V.
AB - In this paper, we propose a processor which is optimized for idle mode operation of a software defined radio (SDR.) terminal. Since a SDR terminal spends most of its time in the idle mode, reducing the power consumption in this mode directly translates to longer terminal standby time. Workload analysis of idle mode operations of contemporary standards showed that these are dominated by FIR filtering, which can be easily parallelized. This analysis was used in the design of the idle mode processor. The key architectural components are an SIMD unit for the parallel computations that dominate the workload, a conventional scalar unit for the sequential computations, and a control unit which supports efficient data memory access and loop control. The idle mode processor was modeled with Verilog and synthesized using standard cells in 0.13 micron technology. It consumes about 9mW at 1.08V.
KW - Baseband processor
KW - Idle mode
KW - Low power
KW - SDR
KW - SIMD
KW - Software defined radio
KW - Wireless terminal
UR - http://www.scopus.com/inward/record.url?scp=34247182545&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34247182545&partnerID=8YFLogxK
U2 - 10.1145/1165573.1165597
DO - 10.1145/1165573.1165597
M3 - Conference contribution
AN - SCOPUS:34247182545
SN - 1595934626
SN - 9781595934628
VL - 2006
SP - 101
EP - 106
BT - Proceedings of the International Symposium on Low Power Electronics and Design
ER -