Abstract
Hardware/Software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. The heuristic aims at maximizing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. The effectiveness of the proposed technique is demonstrated by experimentation.
| Original language | English (US) |
|---|---|
| Title of host publication | Hardware/Software Codesign - Proceedings of the International Workshop |
| Editors | Anon |
| Place of Publication | Los Alamitos, CA, United States |
| Publisher | IEEE Comp Soc |
| Pages | 139-143 |
| Number of pages | 5 |
| State | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 6th International Workshop on Hardware/Software Codesign - Seattle, WA, USA Duration: Mar 15 1998 → Mar 18 1998 |
Other
| Other | Proceedings of the 1998 6th International Workshop on Hardware/Software Codesign |
|---|---|
| City | Seattle, WA, USA |
| Period | 3/15/98 → 3/18/98 |
ASJC Scopus subject areas
- Hardware and Architecture