RECOD: A retiming heuristic to optimize resource and memory utilization in HW/SW codesigns

Karam S. Chatha, Ranga Vemuri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Hardware/Software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. The heuristic aims at maximizing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. The effectiveness of the proposed technique is demonstrated by experimentation.

Original languageEnglish (US)
Title of host publicationHardware/Software Codesign - Proceedings of the International Workshop
Editors Anon
Place of PublicationLos Alamitos, CA, United States
PublisherIEEE Comp Soc
Pages139-143
Number of pages5
StatePublished - 1998
Externally publishedYes
EventProceedings of the 1998 6th International Workshop on Hardware/Software Codesign - Seattle, WA, USA
Duration: Mar 15 1998Mar 18 1998

Other

OtherProceedings of the 1998 6th International Workshop on Hardware/Software Codesign
CitySeattle, WA, USA
Period3/15/983/18/98

ASJC Scopus subject areas

  • Hardware and Architecture

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    Chatha, K. S., & Vemuri, R. (1998). RECOD: A retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. In Anon (Ed.), Hardware/Software Codesign - Proceedings of the International Workshop (pp. 139-143). IEEE Comp Soc.