Real-time Network-on-Chip simulation modeling

Soroosh Gholami, Hessam Sarjoughian

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

We present a Network on Chip (NoC) model with basic support for execution in constrained real-time. Actions for the processing element, switch, network interface, and channel components of NoC are specified in RT-DEVS, an extension of the DEVS formalism for real-time modeling. A desirable simulator must execute the actions defined in each NoC component within finite time periods. Execution of components' actions is supported by introducing a new capability to the DEVS-Suite simulator such that actions can be executed in real-time. The extended simulator can be used to develop, simulate, and evaluate the class of NoC designs that the underlying computing platform can support. NoC simulation can be used to obtain measurements such as system throughput and latency metrics under different communication patterns. This work offers a basis for future research where a NoC simulation can be embedded in a physical environment and thus enable NoC application designs and experimentations.

Original languageEnglish (US)
Title of host publicationSIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques
PublisherICST
Pages103-112
Number of pages10
ISBN (Print)9781450315104
DOIs
StatePublished - 2012
Event5th International Conference on Simulation Tools and Techniques, SIMUTools 2012 - Desenzano del Garda, Italy
Duration: Mar 19 2012Mar 23 2012

Other

Other5th International Conference on Simulation Tools and Techniques, SIMUTools 2012
CountryItaly
CityDesenzano del Garda
Period3/19/123/23/12

Fingerprint

Simulation Modeling
Real-time
Computer simulation
Simulator
Simulators
Network on chip
Network-on-chip
Experimentation
Interfaces (computer)
Latency
Switch
Simulation
Throughput
Switches
Metric
Computing
Evaluate
Communication
Processing
Modeling

Keywords

  • DEVS-suite simulator
  • Network on chip
  • Real-time DEVS modeling

ASJC Scopus subject areas

  • Modeling and Simulation

Cite this

Gholami, S., & Sarjoughian, H. (2012). Real-time Network-on-Chip simulation modeling. In SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques (pp. 103-112). ICST. https://doi.org/10.4108/icst.simutools.2012.247797

Real-time Network-on-Chip simulation modeling. / Gholami, Soroosh; Sarjoughian, Hessam.

SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques. ICST, 2012. p. 103-112.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gholami, S & Sarjoughian, H 2012, Real-time Network-on-Chip simulation modeling. in SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques. ICST, pp. 103-112, 5th International Conference on Simulation Tools and Techniques, SIMUTools 2012, Desenzano del Garda, Italy, 3/19/12. https://doi.org/10.4108/icst.simutools.2012.247797
Gholami S, Sarjoughian H. Real-time Network-on-Chip simulation modeling. In SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques. ICST. 2012. p. 103-112 https://doi.org/10.4108/icst.simutools.2012.247797
Gholami, Soroosh ; Sarjoughian, Hessam. / Real-time Network-on-Chip simulation modeling. SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques. ICST, 2012. pp. 103-112
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