TY - GEN
T1 - Real-time Network-on-Chip simulation modeling
AU - Gholami, Soroosh
AU - Sarjoughian, Hessam
N1 - Publisher Copyright:
© 2012 ICST.
PY - 2012
Y1 - 2012
N2 - We present a Network on Chip (NoC) model with basic support for execution in constrained real-time. Actions for the processing element, switch, network interface, and channel components of NoC are specified in RT-DEVS, an extension of the DEVS formalism for real-time modeling. A desirable simulator must execute the actions defined in each NoC component within finite time periods. Execution of components' actions is supported by introducing a new capability to the DEVS-Suite simulator such that actions can be executed in real-time. The extended simulator can be used to develop, simulate, and evaluate the class of NoC designs that the underlying computing platform can support. NoC simulation can be used to obtain measurements such as system throughput and latency metrics under different communication patterns. This work offers a basis for future research where a NoC simulation can be embedded in a physical environment and thus enable NoC application designs and experimentations.
AB - We present a Network on Chip (NoC) model with basic support for execution in constrained real-time. Actions for the processing element, switch, network interface, and channel components of NoC are specified in RT-DEVS, an extension of the DEVS formalism for real-time modeling. A desirable simulator must execute the actions defined in each NoC component within finite time periods. Execution of components' actions is supported by introducing a new capability to the DEVS-Suite simulator such that actions can be executed in real-time. The extended simulator can be used to develop, simulate, and evaluate the class of NoC designs that the underlying computing platform can support. NoC simulation can be used to obtain measurements such as system throughput and latency metrics under different communication patterns. This work offers a basis for future research where a NoC simulation can be embedded in a physical environment and thus enable NoC application designs and experimentations.
KW - DEVS-suite simulator
KW - Network on chip
KW - Real-time DEVS modeling
UR - http://www.scopus.com/inward/record.url?scp=84876826336&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876826336&partnerID=8YFLogxK
U2 - 10.4108/icst.simutools.2012.247797
DO - 10.4108/icst.simutools.2012.247797
M3 - Conference contribution
AN - SCOPUS:84876826336
T3 - SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques
SP - 103
EP - 112
BT - SIMUTools 2012 - 5th International Conference on Simulation Tools and Techniques
A2 - Himmelspach, Jan
A2 - Quaglia, Francesco
A2 - Riley, George
PB - ICST
T2 - 5th International Conference on Simulation Tools and Techniques, SIMUTools 2012
Y2 - 19 March 2012 through 23 March 2012
ER -