A dual time-constant rail clamp for protecting CMOS circuits during electrostatic discharge (ESD) events is described. In the new circuit, a relatively small time constant is dynamically adjusted after the clamp is triggered during the ESD event, to keep the clamp conducting and dissipate the full ESD energy. The design is area-efficient, can support applications with power-on times as fast as 200 ns, is immune to lock-on during normal powered-on operation, and corrects very quickly when accidentally triggered. The circuit is able to maintain robust performance over industry standard process, voltage, and temperature (PVT) conditions. Experimental results from fabricated silicon die and performance comparisons with the traditional circuit are presented.
- CMOS integrated circuits
- ESD protection design
- and temperature (PVT) variation
- electrostatic discharge (ESD)
- rail clamp
ASJC Scopus subject areas
- Electrical and Electronic Engineering