Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design

Zhiwei Li, Pai Yu Chen, Haijun Liu, Qingjiang Li, Hui Xu, Shimeng Yu

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the limiting factors for building large-scale V-RRAM arrays. The previous approach to evaluate the write/read margin of V-RRAM was based on the exhaustive SPICE simulations, which prohibits the design exploration to MB-level as it takes huge amount of computation resources. In this paper, a quasi-analytical model is proposed, which aims to reduce the simulation time and the required memory usage. Through the validation with the SPICE simulation results, the proposed model shows a similar accuracy. Based on the proposed quasi-analytical model, the worst case data pattern of 3-D V-RRAM with large array size up to 4 MB is analyzed. The results show that it is more efficient to increase the number of stack layers than expanding the horizontal array size to achieve large subarray size.

Original languageEnglish (US)
Article number7859466
Pages (from-to)1568-1574
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume64
Issue number4
DOIs
StatePublished - Apr 1 2017

Keywords

  • 3-D integration
  • Cross-point array
  • Data pattern
  • Nonlinearity
  • Resistive random access memory (RRAM)
  • Sneak path

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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