Quantum transport simulation of Si FinFET: Approaching optimal characteristics for 10 nm high performance devices

H. Khan, D. Mamaluy, Dragica Vasileska

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We utilize fully self-consistent quantum mechanical simulator based on Contact Block Reduction (CBR) method [1] to optimize 10 nm FinFET device to meet ITRS requirements for High Performance (HP) Double-Gate (DG) devices. Fin width, gate oxide thickness, and doping profile are chosen to reflect realistic values and to boost on-current while keeping the total leakage within reasonable limits. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. Small signal analysis has been performed to extract device capacitances. Sensitivity of device performance to the process variation at room temperature has been investigated.

Original languageEnglish (US)
Title of host publication2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings
Pages181-184
Number of pages4
StatePublished - Aug 24 2007
Event2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007 - Santa Clara, CA, United States
Duration: May 20 2007May 24 2007

Publication series

Name2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings
Volume1

Other

Other2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007
CountryUnited States
CitySanta Clara, CA
Period5/20/075/24/07

Keywords

  • CBR
  • Cut-off frequency
  • FinFET
  • Process variation
  • Switching speed

ASJC Scopus subject areas

  • Mechanical Engineering

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  • Cite this

    Khan, H., Mamaluy, D., & Vasileska, D. (2007). Quantum transport simulation of Si FinFET: Approaching optimal characteristics for 10 nm high performance devices. In 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings (pp. 181-184). (2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings; Vol. 1).