Quality-of-service and error control techniques for network-on-chip architectures

Praveen Vellanki; Nilanjan Banerjee; Karam S. Chatha

doi:10.1145/988952.988964

Quality-of-service and error control techniques for network-on-chip architectures

Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

35 Scopus citations

Abstract

Networks-on-a-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Real-time applications require multiple service levels to account for traffic with law delay jitter. As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, that are likely to reduce the reliability of data. This paper addresses two important aspects of NoC architecture, QoS (Quality of Service) and Error Control and makes the following contributions: (i) It presents techniques for supporting guaranteed throughput and best-effort traffic quality levels in NoC router, (ii) It provides models for integrating error control schemes in the NoC router architecture, and (iii) It presents cycle accurate power and performance models of the two architecture enhancements for a 4×4 mesh based NoC architecture.

Original language	English (US)
Title of host publication	Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publication	VLSI in the Nanometer Era
Publisher	Association for Computing Machinery
Pages	45-50
Number of pages	6
ISBN (Print)	1581138539, 9781581138535
DOIs	https://doi.org/10.1145/988952.988964
State	Published - 2004
Event	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States Duration: Apr 26 2004 → Apr 28 2004

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI

Other

Other	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country/Territory	United States
City	Boston, MA
Period	4/26/04 → 4/28/04

Keywords

Error detection & correction
Interconnection networks
Networks-on-Chip
Performance
Power
Quality-of-Service

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/988952.988964

Cite this

Vellanki, P., Banerjee, N., & Chatha, K. S. (2004). Quality-of-service and error control techniques for network-on-chip architectures. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 45-50). (Proceedings of the ACM Great Lakes Symposium on VLSI). Association for Computing Machinery. https://doi.org/10.1145/988952.988964

Quality-of-service and error control techniques for network-on-chip architectures. / Vellanki, Praveen; Banerjee, Nilanjan; Chatha, Karam S.
Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Association for Computing Machinery, 2004. p. 45-50 (Proceedings of the ACM Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Vellanki, P, Banerjee, N & Chatha, KS 2004, Quality-of-service and error control techniques for network-on-chip architectures. in Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Proceedings of the ACM Great Lakes Symposium on VLSI, Association for Computing Machinery, pp. 45-50, Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, Boston, MA, United States, 4/26/04. https://doi.org/10.1145/988952.988964

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abstract = "Networks-on-a-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Real-time applications require multiple service levels to account for traffic with law delay jitter. As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, that are likely to reduce the reliability of data. This paper addresses two important aspects of NoC architecture, QoS (Quality of Service) and Error Control and makes the following contributions: (i) It presents techniques for supporting guaranteed throughput and best-effort traffic quality levels in NoC router, (ii) It provides models for integrating error control schemes in the NoC router architecture, and (iii) It presents cycle accurate power and performance models of the two architecture enhancements for a 4×4 mesh based NoC architecture.",

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AB - Networks-on-a-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Real-time applications require multiple service levels to account for traffic with law delay jitter. As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, that are likely to reduce the reliability of data. This paper addresses two important aspects of NoC architecture, QoS (Quality of Service) and Error Control and makes the following contributions: (i) It presents techniques for supporting guaranteed throughput and best-effort traffic quality levels in NoC router, (ii) It provides models for integrating error control schemes in the NoC router architecture, and (iii) It presents cycle accurate power and performance models of the two architecture enhancements for a 4×4 mesh based NoC architecture.

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Quality-of-service and error control techniques for network-on-chip architectures

Abstract

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Keywords

ASJC Scopus subject areas

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