Quality-of-service and error control techniques for network-on-chip architectures

Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Scopus citations

Abstract

Networks-on-a-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Real-time applications require multiple service levels to account for traffic with law delay jitter. As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, that are likely to reduce the reliability of data. This paper addresses two important aspects of NoC architecture, QoS (Quality of Service) and Error Control and makes the following contributions: (i) It presents techniques for supporting guaranteed throughput and best-effort traffic quality levels in NoC router, (ii) It provides models for integrating error control schemes in the NoC router architecture, and (iii) It presents cycle accurate power and performance models of the two architecture enhancements for a 4×4 mesh based NoC architecture.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
PublisherAssociation for Computing Machinery
Pages45-50
Number of pages6
ISBN (Print)1581138539, 9781581138535
DOIs
StatePublished - 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: Apr 26 2004Apr 28 2004

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI

Other

OtherProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
CountryUnited States
CityBoston, MA
Period4/26/044/28/04

Keywords

  • Error detection & correction
  • Interconnection networks
  • Networks-on-Chip
  • Performance
  • Power
  • Quality-of-Service

ASJC Scopus subject areas

  • Engineering(all)

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    Vellanki, P., Banerjee, N., & Chatha, K. S. (2004). Quality-of-service and error control techniques for network-on-chip architectures. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 45-50). (Proceedings of the ACM Great Lakes Symposium on VLSI). Association for Computing Machinery. https://doi.org/10.1145/988952.988964