Abstract
Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by developing two layout strategies for rectangular grids. Then, two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. We demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.
| Original language | English (US) |
|---|---|
| Title of host publication | Proc Second Great Lakes Symp VLSI |
| Place of Publication | Los Alamitos, CA, United States |
| Publisher | Publ by IEEE |
| Pages | 74-81 |
| Number of pages | 8 |
| State | Published - 1991 |
| Externally published | Yes |
| Event | Proceedings of the Second Great Lakes Symposium on VLSI - Kalamazoo, MI, USA Duration: Feb 28 1992 → Feb 29 1992 |
Other
| Other | Proceedings of the Second Great Lakes Symposium on VLSI |
|---|---|
| City | Kalamazoo, MI, USA |
| Period | 2/28/92 → 2/29/92 |
ASJC Scopus subject areas
- General Engineering