TY - GEN
T1 - Programming strategies to improve energy efficiency and reliability of ReRAM memory systems
AU - Mao, Manqing
AU - Cao, Yu
AU - Yu, Shimeng
AU - Chakrabarti, Chaitali
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/12/2
Y1 - 2015/12/2
N2 - Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM for main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ultra-high density ReRAM cross-point array. In this paper, we propose several novel write strategies for 1T1R ReRAM aiming at high performance, low power and high reliability. We reduce the write latency significantly compared to the baseline scheme by using the same WL voltages and improve energy consumption and endurance by choosing proper set line, bit line and word line settings. The SPICE simulation results demonstrate that appropriate choice of circuit operation parameters can help obtain 10× improvement in lifetime with 33.6% reduction in energy compared to the baseline. Also, among all proposed systems, configurations which consume higher write energy also have higher endurance. We evaluate the system-level parameters of a 1GB ReRAM memory using CACTI and GEM5. We show that all the proposed ReRAM systems can achieve a lifetime of 30 years by employing error control coding (ECC). Finally, we show that the ReRAM based main memory can outperform DRAM main memory with respect to IPC (5.5% higher) and energy consumption (39.4% lower) through proper choice of write scheme configurations.
AB - Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM for main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ultra-high density ReRAM cross-point array. In this paper, we propose several novel write strategies for 1T1R ReRAM aiming at high performance, low power and high reliability. We reduce the write latency significantly compared to the baseline scheme by using the same WL voltages and improve energy consumption and endurance by choosing proper set line, bit line and word line settings. The SPICE simulation results demonstrate that appropriate choice of circuit operation parameters can help obtain 10× improvement in lifetime with 33.6% reduction in energy compared to the baseline. Also, among all proposed systems, configurations which consume higher write energy also have higher endurance. We evaluate the system-level parameters of a 1GB ReRAM memory using CACTI and GEM5. We show that all the proposed ReRAM systems can achieve a lifetime of 30 years by employing error control coding (ECC). Finally, we show that the ReRAM based main memory can outperform DRAM main memory with respect to IPC (5.5% higher) and energy consumption (39.4% lower) through proper choice of write scheme configurations.
KW - 1T1R ReRAM
KW - IPC
KW - energy
KW - latency
KW - main memory
KW - reliability
UR - http://www.scopus.com/inward/record.url?scp=84958212264&partnerID=8YFLogxK
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U2 - 10.1109/SiPS.2015.7344980
DO - 10.1109/SiPS.2015.7344980
M3 - Conference contribution
AN - SCOPUS:84958212264
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
BT - Electronic Proceedings of the 2015 IEEE International Workshop on Signal Processing Systems, SiPS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Workshop on Signal Processing Systems, SiPS 2015
Y2 - 14 October 2015 through 16 October 2015
ER -