Abstract

Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM for main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ultra-high density ReRAM cross-point array. In this paper, we propose several novel write strategies for 1T1R ReRAM aiming at high performance, low power and high reliability. We reduce the write latency significantly compared to the baseline scheme by using the same WL voltages and improve energy consumption and endurance by choosing proper set line, bit line and word line settings. The SPICE simulation results demonstrate that appropriate choice of circuit operation parameters can help obtain 10× improvement in lifetime with 33.6% reduction in energy compared to the baseline. Also, among all proposed systems, configurations which consume higher write energy also have higher endurance. We evaluate the system-level parameters of a 1GB ReRAM memory using CACTI and GEM5. We show that all the proposed ReRAM systems can achieve a lifetime of 30 years by employing error control coding (ECC). Finally, we show that the ReRAM based main memory can outperform DRAM main memory with respect to IPC (5.5% higher) and energy consumption (39.4% lower) through proper choice of write scheme configurations.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-December
ISBN (Print)9781467396042
DOIs
StatePublished - Dec 2 2015
EventIEEE International Workshop on Signal Processing Systems, SiPS 2015 - Hangzhou, China
Duration: Oct 14 2015Oct 16 2015

Other

OtherIEEE International Workshop on Signal Processing Systems, SiPS 2015
CountryChina
CityHangzhou
Period10/14/1510/16/15

Keywords

  • 1T1R ReRAM
  • energy
  • IPC
  • latency
  • main memory
  • reliability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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  • Cite this

    Mao, M., Cao, Y., Yu, S., & Chakrabarti, C. (2015). Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (Vol. 2015-December). [7344980] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SiPS.2015.7344980