Programmable ANalog Device Array (PANDA): A methodology for transistor-level analog emulation

Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).

Original languageEnglish (US)
Article number6516619
Pages (from-to)1369-1380
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number6
DOIs
StatePublished - 2013

Fingerprint

Transistors
Bias currents
Operational amplifiers
Variable frequency oscillators
Rapid prototyping
Switches
Hardware
Degradation
Silicon
Networks (circuits)
Testing
Costs
Analog integrated circuits

Keywords

  • Automation
  • FPAA
  • FPGA
  • hardware emulation
  • programmable
  • rapid prototyping
  • reconfigurable analog design
  • scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Programmable ANalog Device Array (PANDA) : A methodology for transistor-level analog emulation. / Suh, Jounghyuk; Suda, Naveen; Xu, Cheng; Hakim, Nagib; Cao, Yu; Bakkaloglu, Bertan.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 6, 6516619, 2013, p. 1369-1380.

Research output: Contribution to journalArticle

@article{585c525f97dd4ac69b09d22293d88772,
title = "Programmable ANalog Device Array (PANDA): A methodology for transistor-level analog emulation",
abstract = "The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5{\%} for ID and less than 10{\%} for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5{\%} error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).",
keywords = "Automation, FPAA, FPGA, hardware emulation, programmable, rapid prototyping, reconfigurable analog design, scaling",
author = "Jounghyuk Suh and Naveen Suda and Cheng Xu and Nagib Hakim and Yu Cao and Bertan Bakkaloglu",
year = "2013",
doi = "10.1109/TCSI.2012.2220453",
language = "English (US)",
volume = "60",
pages = "1369--1380",
journal = "IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

TY - JOUR

T1 - Programmable ANalog Device Array (PANDA)

T2 - A methodology for transistor-level analog emulation

AU - Suh, Jounghyuk

AU - Suda, Naveen

AU - Xu, Cheng

AU - Hakim, Nagib

AU - Cao, Yu

AU - Bakkaloglu, Bertan

PY - 2013

Y1 - 2013

N2 - The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).

AB - The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).

KW - Automation

KW - FPAA

KW - FPGA

KW - hardware emulation

KW - programmable

KW - rapid prototyping

KW - reconfigurable analog design

KW - scaling

UR - http://www.scopus.com/inward/record.url?scp=84878410605&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84878410605&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2012.2220453

DO - 10.1109/TCSI.2012.2220453

M3 - Article

AN - SCOPUS:84878410605

VL - 60

SP - 1369

EP - 1380

JO - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

JF - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

SN - 1549-8328

IS - 6

M1 - 6516619

ER -