Process scalability of pulse-based circuits for analog image convolution

Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale

Research output: Contribution to journalArticle

Abstract

This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model.

Original languageEnglish (US)
Article number8341826
Pages (from-to)2929-2938
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number9
DOIs
StatePublished - Sep 2018

Keywords

  • Time-mode circuits
  • convolution
  • neuromorphic circuits
  • spiking neurons

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    D'Angelo, R., Du, X., Salthouse, C. D., Hollosi, B., Freifeld, G., Uy, W., Huang, H., Tran, N., Chery, A., Seo, J., Cao, Y., Poppe, D. C., & Sonkusale, S. R. (2018). Process scalability of pulse-based circuits for analog image convolution. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(9), 2929-2938. [8341826]. https://doi.org/10.1109/TCSI.2018.2821691