Probability distribution of signal arrival times using Bayesian networks

Sarvesh Bhardwaj, Sarma Vrudhula, David Blaauw

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a new method based on Bayesian networks (BNs) for computing the exact probability distribution of the delay of a circuit. The method is based on BNs, which allows an efficient means to factor the joint probability distributions over variables in a circuit graph. The space complexity of the method presented here is O(m |C|), where m is the number of distinct values taken by each delay variable and |C| is the number of variables in the largest clique. The maximum clique size present in a BN is shown to be much smaller than the circuit size. For large circuits, where it is not practically feasible to compute the exact distribution, methods to reduce the problem size and get a lower bound on the exact distribution are presented. Comparison of the results with Monte Carlo simulations shows that we can reduce the size of the circuit by as much as 89% while maintaining the maximum difference between the predicted and simulated 3σ values to be less than 3%.

Original languageEnglish (US)
Pages (from-to)1784-1794
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume24
Issue number11
DOIs
StatePublished - Nov 2005

Fingerprint

Bayesian networks
Probability distributions
Networks (circuits)

Keywords

  • Bayesian networks
  • Probability
  • Process variations
  • Timing
  • Yield estimation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

Probability distribution of signal arrival times using Bayesian networks. / Bhardwaj, Sarvesh; Vrudhula, Sarma; Blaauw, David.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 11, 11.2005, p. 1784-1794.

Research output: Contribution to journalArticle

@article{c9dc1f81ec274c049c82233fcca7da9b,
title = "Probability distribution of signal arrival times using Bayesian networks",
abstract = "This paper presents a new method based on Bayesian networks (BNs) for computing the exact probability distribution of the delay of a circuit. The method is based on BNs, which allows an efficient means to factor the joint probability distributions over variables in a circuit graph. The space complexity of the method presented here is O(m |C|), where m is the number of distinct values taken by each delay variable and |C| is the number of variables in the largest clique. The maximum clique size present in a BN is shown to be much smaller than the circuit size. For large circuits, where it is not practically feasible to compute the exact distribution, methods to reduce the problem size and get a lower bound on the exact distribution are presented. Comparison of the results with Monte Carlo simulations shows that we can reduce the size of the circuit by as much as 89{\%} while maintaining the maximum difference between the predicted and simulated 3σ values to be less than 3{\%}.",
keywords = "Bayesian networks, Probability, Process variations, Timing, Yield estimation",
author = "Sarvesh Bhardwaj and Sarma Vrudhula and David Blaauw",
year = "2005",
month = "11",
doi = "10.1109/TCAD.2005.852436",
language = "English (US)",
volume = "24",
pages = "1784--1794",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - Probability distribution of signal arrival times using Bayesian networks

AU - Bhardwaj, Sarvesh

AU - Vrudhula, Sarma

AU - Blaauw, David

PY - 2005/11

Y1 - 2005/11

N2 - This paper presents a new method based on Bayesian networks (BNs) for computing the exact probability distribution of the delay of a circuit. The method is based on BNs, which allows an efficient means to factor the joint probability distributions over variables in a circuit graph. The space complexity of the method presented here is O(m |C|), where m is the number of distinct values taken by each delay variable and |C| is the number of variables in the largest clique. The maximum clique size present in a BN is shown to be much smaller than the circuit size. For large circuits, where it is not practically feasible to compute the exact distribution, methods to reduce the problem size and get a lower bound on the exact distribution are presented. Comparison of the results with Monte Carlo simulations shows that we can reduce the size of the circuit by as much as 89% while maintaining the maximum difference between the predicted and simulated 3σ values to be less than 3%.

AB - This paper presents a new method based on Bayesian networks (BNs) for computing the exact probability distribution of the delay of a circuit. The method is based on BNs, which allows an efficient means to factor the joint probability distributions over variables in a circuit graph. The space complexity of the method presented here is O(m |C|), where m is the number of distinct values taken by each delay variable and |C| is the number of variables in the largest clique. The maximum clique size present in a BN is shown to be much smaller than the circuit size. For large circuits, where it is not practically feasible to compute the exact distribution, methods to reduce the problem size and get a lower bound on the exact distribution are presented. Comparison of the results with Monte Carlo simulations shows that we can reduce the size of the circuit by as much as 89% while maintaining the maximum difference between the predicted and simulated 3σ values to be less than 3%.

KW - Bayesian networks

KW - Probability

KW - Process variations

KW - Timing

KW - Yield estimation

UR - http://www.scopus.com/inward/record.url?scp=27744597124&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=27744597124&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2005.852436

DO - 10.1109/TCAD.2005.852436

M3 - Article

AN - SCOPUS:27744597124

VL - 24

SP - 1784

EP - 1794

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 11

ER -