TY - JOUR
T1 - Probabilistic analysis of interconnect coupling noise
AU - Vrudhula, Sarma
AU - Blaauw, David T.
AU - Sirichotiyakul, Supamas
N1 - Funding Information:
Manuscript received July 25, 2001; revised January 28, 2002 and July 30, 2002. This work was supported in part by the National Science Foundation Center for Low Power Electronics under Grant EEC-9523338 and in part by the National Science Foundation under Grant CCR-0205227. This paper was recommended by Associate Editor M. Pedram.
PY - 2003/9
Y1 - 2003/9
N2 - Noise simulators and noise avoidance tools are playing an increasingly critical role in the design of deep submicron circuits. However, noise estimates produced by these simulators are often very pessimistic. For large, high-performance industrial ICs, which can contain hundreds of thousands of nets, the worst case estimates of the noise results in thousands of reported violations, without any information about the likelihood of the possible noise violation. In this paper, we present a probabilistic approach to prioritize the violating nets based on the likelihood of occurrence of the reported noise. We derive an upper bound on the probability that the total noise injected on a given victim net by a specific set of aggressors exceeds a threshold. This is equivalent to a lower bound on the expected number of clock cycles required to realize the noise violation for the first time, i.e., mean time-to-failure. If the probability of a failure in a victim is sufficiently small, it is possible that even during the operation of the part for a number of years, the probability of failure on the net is negligible and the net can be assigned a lower priority for the application of noise avoidance strategies. We demonstrate the utility of this approach through experiments carried out on an large industrial processor design using a state-of-the-art industrial noise analysis tool.
AB - Noise simulators and noise avoidance tools are playing an increasingly critical role in the design of deep submicron circuits. However, noise estimates produced by these simulators are often very pessimistic. For large, high-performance industrial ICs, which can contain hundreds of thousands of nets, the worst case estimates of the noise results in thousands of reported violations, without any information about the likelihood of the possible noise violation. In this paper, we present a probabilistic approach to prioritize the violating nets based on the likelihood of occurrence of the reported noise. We derive an upper bound on the probability that the total noise injected on a given victim net by a specific set of aggressors exceeds a threshold. This is equivalent to a lower bound on the expected number of clock cycles required to realize the noise violation for the first time, i.e., mean time-to-failure. If the probability of a failure in a victim is sufficiently small, it is possible that even during the operation of the part for a number of years, the probability of failure on the net is negligible and the net can be assigned a lower priority for the application of noise avoidance strategies. We demonstrate the utility of this approach through experiments carried out on an large industrial processor design using a state-of-the-art industrial noise analysis tool.
KW - Capacitive coupling
KW - Crosstalk noise
KW - Functional noise
KW - Interconnect analysis
KW - Noise estimation
UR - http://www.scopus.com/inward/record.url?scp=0141628933&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0141628933&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2003.816212
DO - 10.1109/TCAD.2003.816212
M3 - Article
AN - SCOPUS:0141628933
SN - 0278-0070
VL - 22
SP - 1188
EP - 1203
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
ER -